Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2006-02-27
2009-10-20
Peugh, Brian R (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S143000, C711S126000, C714S006130
Reexamination Certificate
active
07606980
ABSTRACT:
A technique for demand-based error correction. More particularly, at least one embodiment of the invention relates to a technique to reduce storage overhead of cache memories containing error correction codes (ECC) while maintaining substantially the same performance of the cache.
REFERENCES:
patent: 6480975 (2002-11-01), Arimilli et al.
patent: 7219185 (2007-05-01), Luick
patent: 7437597 (2008-10-01), Kruckemyer et al.
patent: 2002/0032891 (2002-03-01), Yada et al.
Gharachorloo et al., Efficient ECC-Based Directory Implementations for Scalable Multiprocessors, 12thsymposium on Computer Architecture and High-Performance Computing, Oct. 2000.
Mukherjee Shubhendu S.
Qureshi Moinuddin K.
Racunas Paul B.
Caven & Aghevli LLC
Intel Corporation
Peugh Brian R
Rutz Jared I
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