Datapipe CPU register array

Daughtercard-based system software and hardware...

Deadlock avoidance in a bus fabric

Deadlock avoidance in a bus fabric

Deadlock-resistant bus bridge with pipeline-restricted...

DEBUG mode for a data bus

Debugging multi-port bridge system conforming to serial...

Decoder-based circuitry for sharing an interrupt between...

Decoding method for reducing delay time

Decoupling unit for bus systems that blocks abnormal...

Dedicated circuit and method for enumerating and operating a...

Dedication of space in descriptor for minimizing data...

Default bus grant to a bus agent

Deferring peripheral traffic with sideband control

Deferring peripheral traffic with sideband control

Delay data block release system in a disk drive

Delayed memory access request arbitration

Delayed transaction method and device used in a PCI system

Delegating network processor operations to star topology...

Delegating network processor operations to star topology...