Deadlock-resistant bus bridge with pipeline-restricted...

Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture

Reexamination Certificate

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Details

C710S009000, C710S039000, C710S306000, C710S311000, C710S004000, C711S200000, C711S202000

Reexamination Certificate

active

07970977

ABSTRACT:
A method of bridging a plurality of buses within a bus bridge can include determining whether a queue of the bus bridge includes a transaction request directed to a restricted address range and, for each received transaction request, determining whether an address to which the transaction request is directed is within the restricted address range. Each transaction request received by the bus bridge can be selectively rejected according to whether the address to which the transaction request is directed is within the restricted address range and whether the queue includes a transaction request directed to the restricted address range.

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patent: 6880035 (2005-04-01), Groeger et al.
patent: 6901451 (2005-05-01), Miyoshi et al.
patent: 7035958 (2006-04-01), Augsburg et al.
patent: 7315912 (2008-01-01), Reed
patent: 7412555 (2008-08-01), Wang
patent: 7469309 (2008-12-01), Duncan et al.
patent: 7694025 (2010-04-01), Norrie

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