PCI-X error correcting code (ECC) pin sharing configuration
Peer-to-peer bus segment bridging
Performance based packet ordering in a PCI express bus
Performance of a PCI-X to infiniband bridge
Performing an N-bit write access to an M×N-bit-only...
Performing an N-bit write access to an M×N-bit-only...
Peripheral bus extender
Peripheral bus jumper block for a configurable peripheral...
Peripheral bus switch having virtual peripheral bus and...
Peripheral bus switch to maintain continuous peripheral bus...
Peripheral component interconnect (PCI) configuration...
PERIPHERAL COMPONENT INTERCONNECT BUS DETECTION IN LOGICALLY...
Peripheral component interface with multiple data channels...
Peripheral device with shared bus interface and operating...
Peripheral switching device with multiple sets of registers...
Peripherals of computer
Peripherals of computer
Peripherals of computer
Phase manipulation of intertwined bus signals for reduction...
Physical layer and data link interface with flexible bus width