PERIPHERAL COMPONENT INTERCONNECT BUS DETECTION IN LOGICALLY...

Details PERIPHERAL COMPONENT INTERCONNECT BUS DETECTION IN LOGICALLY... PERIPHERAL COMPONENT INTERCONNECT BUS DETECTION IN LOGICALLY...

2001-04-17

2004-11-16

Myers, Paul R. (Department: 2111)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus interface architecture

C710S314000, C710S008000, C710S002000

Reexamination Certificate

active

06820164

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a detection of PCI buses in partitioned computer systems.
2. Description of the Related Art
In logically partitioned computer systems, multiple distinct individual operating systems generally share a single computer hardware structure. Although the various operating systems share a single supporting hardware structure, the individual operating systems may run simultaneously and autonomously within their respective partitioned environments. In order to control and/or manage the multitude of operating systems in the various partitioned environments, a single global software system and/or firmware component, which may be termed a hypervisor, is generally utilized. The hypervisor is generally configured to manage and/or control the allocation/use of the resources available on the single computer hardware system by each of the respective operating systems. For example, the hypervisor may control resource access and allocation for the overall computer system data storage mediums, access to the available system CPUs, and/or any of the system input/output (IO) device adapters, along with other known features of computer systems. The hypervisor may be further configured to insure that the respective individual partitions are unaware of the existence of each other and do not interfere with their respective operations. In this type of logically partitioned system using a hypervisor, it is desirable to allow different partitions to share the respective IO buses, while maintaining exclusive ownership/control over the individual IO device adapters in communication with the IO buses.
A peripheral component interconnect (PCI) bus is an industry standard IO bus that is widely used in computer systems ranging from typical desktop systems running Microsoft Windows-type operating systems to open-source Linux based systems and large mainframe class computers, such as the IBM AS400/iSeries and RS6000/pSeries computers running OS400 and AIX, respectively. The PCI IO bus implemented in these types of systems is generally in communication with a computer system central processing unit (CPU) and/or memory complex via a PCI host bridge (PHB). Additionally, the PCI IO bus is generally in communication with a plurality of PCI-type devices. The specific types of IO devices may include IO device adapters that are configured to connect a given IO device type, i.e., a disk-type storage medium, a tape drive, or a network connection, for example, to the PCI bus. Further, a PCI bus may be in communication with additional PCI and/or other IO buses via a PCI bridge device in a structured tree-type hierarchy configuration, which may allow for substantial IO device density expansion. The additional PCI buses are generally positioned below the PHB and may be in communication with the root PCI bus. Therefore, in view of this configuration, the PHB may generally operate as an originating or root PCI bus of a tree of PCI devices and/or a combination of PCI and/or other IO buses. In smaller computer systems there may be only one or two PHBs connected to the memory bus, whereas larger more complex computer systems, such as those that are generally capable of logical partitioning-type functions, may have upwards of several hundred PHBs connected to the computer memory bus. The management of this quantity of PHBs and the accompanying IO devices in communication therewith presents substantial obstacles for the hypervisor.
In many PCI system implementations, such as personal computers (PCs), RS6000 configurations, and/or other workstation class computer systems, a firmware component of the system determines the configuration of the PCI buses and accompanying devices. The firmware may determine the configuration from the system boot programming and/or the initial program load (IPL) process and supporting code. In communications within the system after initialization, the firmware determined system configuration may be transmitted to the operating system and various software/hardware applications subsequently loaded by the firmware so that these applications can utilize the system's determined configuration in their respective initializations. Firmware may be a limited set of hardware configuration programs that reside in a read only-type memory and operate to initialize the computer hardware. The hardware initialization process is generally configured to facilitate the subsequent loading of the complete operating system software, which is generally stored on a readable/writable storage medium. Once the complete operating system is loaded, system control is generally transferred to the complete operating system from the firmware. For example, in a typical PC workstation or server configuration the firmware is referred to as the basic IO subsystem (BIOS) and is considered to be a component of the computer hardware that the computer manufacturer provides. Alternatively, operating system software may be provided by a third party, such as Microsoft Windows or DOS, IBM OS2, or Linux, for example.
In a logically partitioned computer system, a hypervisor program is generally an extension of the basic hardware control firmware of the computer. The hypervisor may operate to manage the partitioning of hardware resources between different operating systems that may be executing within the individual logical partitions. Therefore, in a logically partitioned system the hypervisor program may be thought of as the analog to the PC BIOS or firmware of non-partitioned-type computer systems. The hypervisor may also be configured to initialize only the hardware structure and/or elements that are assigned to particular partitions for those partitions. The computer hardware generally includes programs in a read only-type memory that encapsulates the details of the underlying computer hardware interconnections and control mechanisms. The combination of the hardware interconnections and control mechanisms enable the operating system to view the respective hardware elements as a collection of more abstract hardware elements that then appear similar for various underlying computer hardware implementations. The operating system also commonly includes PCI bus initialization programs that call these programs in the read only memory in order to activate specific hardware controls without direct knowledge of the specific underlying computer hardware interconnections and control mechanisms of the particular computer.
In a computer system using PCI buses, a device driver program executing within a logical partition generally controls the IO devices connected to the PCI bus. The PCI bus implementation generally includes the capability to generate a hardware interrupt signal from a PCI device in order to allow that device to alert the device driver program of a change in the state of the device. For example, an interrupt may be generated upon the completion of a command received from the device driver or at the occurrence of an event that is within the supervisory functions of the device driver. Generally accepted PCI standards specify interrupt signals that are output pins from a PCI device to its PCI bus connection. However, the accepted standards do not specify how these device interrupt outputs are connected to the other hardware elements of the computer system that effect the device driver program interrupt. For example, an interrupt controller that receives a PCI interrupt output signal from a device and causes a CPU interrupt may not be specified in current accepted standards. Generally, the computer hardware provides some form of interrupt controller that receives hardware interrupt outputs from other hardware components, including PCI devices, and generates a CPU interrupt indicating the particular hardware component that signaled the interrupt condition. The Intel Open Programmable Interrupt Controller is an example of an interrupt controller that is in wide use in PC, Workstation, and PC server class computers and that commonly provides 8 or 16 such

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