Performance based packet ordering in a PCI express bus

Details Performance based packet ordering in a PCI express bus Performance based packet ordering in a PCI express bus

2011-03-29

2011-03-29

Knoll, Clifford H (Department: 2111)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus interface architecture

C711S154000

Reexamination Certificate

active

07917680

ABSTRACT:
A communications arrangement is implemented for packet data communications control. According to an example embodiment of the present invention, a communications arrangement (100), such as a PCI Express type arrangement, carries out separate arbitration functions (112, 116, 117, 118) for ordering packet data. One of the arbitration functions (112) orders the packet data in accordance with protocol standards (e.g., to meet PCI Express standards when implemented with a PCI Express system). The other arbitration function (116, 117, 118) orders the packet data in accordance with performance standards while maintaining compliance with the protocol standards.

REFERENCES:
patent: 2004/0064626 (2004-04-01), Shah et al.
patent: 2004/0213152 (2004-10-01), Matuoka et al.
patent: 1531282 (2004-09-01), None
“PCI Express Base Specifications Revision 1.0A”, PCI-SIG, Apr. 2003.
Office Action from Chinese Patent Appln. No. 200580039435.6 (Sep. 11, 2009), w/ English transln.

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