Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
1999-12-23
2004-04-06
Thai, Xuan (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C709S250000, C370S463000
Reexamination Certificate
active
06718417
ABSTRACT:
BACKGROUND
In a system of networked computers, a computer communicates with other computers in the network via a data link or medium. The interface between the medium and the computer is often referred to as a network controller. The network controller interprets data from the computer and modulates an electromagnetic wave that is propagated on the medium in response to the data, and also receives and demodulates electromagnetic waves propagating on the medium in order to provide received data to the computer.
Within the context of the OSI (Open Systems Interconnection) layered communication model of the ISO (international Standards Organization), a network controller provides the function of a DLC (Data Link Control) and a PHY (Physical layer). A standard for a popular network and medium is defined in IEEE (Institute of Electrical and Electronic Engineers) standard 802.3, commonly referred to as Ethernet. Ethernet further divides the DLC so that it includes a MAC (Medium Access Control) sublayer.
In the past, a network controller usually comprised a set of semiconductor components residing on a card. However, with the number of transistors on a die increasing, the level of integration is also increasing. As a result, the MAC usually associated with a network controller may be integrated with the chipset of a personal computer. With such an arrangement, the PHY may be supplied separately by manufacturers other than the manufacturer of the chipset. Consequently, it is desirable that the interface between a MAC and PHY be flexible enough so that PHYs from different manufacturers, with possibly different numbers of pin counts and data link speeds, may be connected to the MAC. It is also desirable that the pin count for such an interface be kept as small as possible without sacrificing flexibility and future requirements.
REFERENCES:
patent: 4525795 (1985-07-01), Rubin
patent: 5088090 (1992-02-01), Yacoby
patent: 5214646 (1993-05-01), Yacoby
patent: 5305317 (1994-04-01), Szczepanek
patent: 5371734 (1994-12-01), Fischer
patent: 5493571 (1996-02-01), Engdahl et al.
patent: 5513320 (1996-04-01), Young et al.
patent: 5592468 (1997-01-01), Sato
patent: 5619652 (1997-04-01), Travaglio
patent: 5635856 (1997-06-01), Raza et al.
patent: 5636140 (1997-06-01), Lee et al.
patent: 5708779 (1998-01-01), Graziano et al.
patent: 5926504 (1999-07-01), Andersson et al.
patent: 5938728 (1999-08-01), Dwork et al.
patent: 5963543 (1999-10-01), Rostokel et al.
patent: 6044087 (2000-03-01), Muller et al.
patent: 6049837 (2000-04-01), Youngman
patent: 6058427 (2000-05-01), Viswanath et al.
patent: 6085248 (2000-07-01), Sambamurthy et al.
patent: 6098103 (2000-08-01), Dreyer et al.
patent: 6108726 (2000-08-01), Runaldue et al.
patent: 6141352 (2000-10-01), Gandy
patent: 6157951 (2000-12-01), Vasa
patent: 6222852 (2001-04-01), Gandy
patent: 6226680 (2001-05-01), Boucher et al.
patent: 6260162 (2001-07-01), Typaldos et al.
patent: 6269104 (2001-07-01), McLaughlin et al.
patent: 6292467 (2001-09-01), Keller et al.
patent: 6295281 (2001-09-01), Itkowsky et al.
patent: 6314501 (2001-11-01), Gullick et al.
patent: 6328480 (2001-12-01), Strike
patent: 6345310 (2002-02-01), Allison et al.
patent: 6363432 (2002-03-01), Laber
patent: 6377640 (2002-04-01), Trans
patent: 6385208 (2002-05-01), Findlater et al.
patent: 6385738 (2002-05-01), Lo
patent: 6427173 (2002-07-01), Boucher et al.
patent: 6516352 (2003-02-01), Booth et al.
patent: WO 98/11696 (1998-03-01), None
Lettierei, Paul et al. Adaptive Frame Length Control for Improving Wireless Link Throughput, Range, and Energy Efficiency.
ANSI/IEEE STD. 802.3 Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method and Physical Layer Specifications, 1085, The Institute of Electrical and Electronics Engineers Inc., 5th printing, pp. 20-56.
Matthew Flint et al. Inside TCP/IP, Second Edition, 11 pages.
Intel Corporation
Kalson Seth Z.
Thai Xuan
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