Method of making polysilicon-via structure for four transistor,

Details Method of making polysilicon-via structure for four transistor, Method of making polysilicon-via structure for four transistor,

1997-10-27

1999-02-02

Chaudhari, Chandra

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438586, 438657, H01L 218244

Patent

active

058664491

ABSTRACT:
This is a method of forming an SRAM transistor cell on a well in a doped semiconductor substrate. Form a gate oxide layer and a split gate layer with buried contact regions in the well and openings through the split gate layer and the gate oxide layer to the well. Form an intermediate conductor layer and a hard silicon oxide mask layer and define gate conductors. Form lightly doped source/drain regions, form spacers and source/drain regions in the well. Form a first inter-conductor dielectric layer on the cell. Define a self-aligned contact region in the cell above source/drain regions. Form a second conductor layer over the cell and patterning the second conductor layer to form a via in the self-aligned contact region. Form a second inter-conductor dielectric layer on the cell, a third conductor layer over the cell and patterning the third conductor layer to form a first resistor connected to the self-aligned contact region.

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patent: 5545584 (1996-08-01), Wuu et al.
patent: 5547892 (1996-08-01), Wuu et al.
patent: 5585302 (1996-12-01), Li

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