Thomas W. S. Thomson

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Can interface with enhanced fault confinement

Patent

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Combined multiplier and accumulator

Boots – shoes – and leggings
Patent

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CPU with integrated multiply/accumulate unit

Boots – shoes – and leggings
Patent

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Layout efficient 32-bit shifter/register with 16-bit interface

Boots – shoes – and leggings
Patent

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Method and system for reducing taken branch penalty

Electrical computers and digital processing systems: processing – Processing control – Branching
Reexamination Certificate

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Profile ID: LFUS-PAI-P-908061

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