Method and system for reducing taken branch penalty

Details Method and system for reducing taken branch penalty Method and system for reducing taken branch penalty

2000-05-01

2004-05-11

Tsai, Henry W. H. (Department: 2183)

Electrical computers and digital processing systems: processing

Processing control

Branching

C712S237000

Reexamination Certificate

active

06735689

ABSTRACT:

FIELD OF INVENTION
Invention relates to microprocessor design and related signal processing circuit and logic, particularly to technique for reducing taken branch penalty by converting branches to jumps.
BACKGROUND OF INVENTION
Conventional microprocessor design employs various logic for causing branching or redirection effectively of instruction or signal processing flow. For example, a target of a taken branch may be calculated from a given offset value relative to an address of the particular branch instruction. However, such calculation requires an additional step, thereby wasting processor cycles and degrading performance. Thus, because branches occur often during program execution, it is desirable to provide improved branching approach.
SUMMARY OF INVENTION
Invention pre-calculates target of conditional branch before branch is encountered, thereby reducing penalty in taking branch in pipelined processor by converting branches to jumps. During program execution, pipeline penalty is reduced effectively to that of unconditional jump. In particular, offset bits may be replaced in conditional branch using index bits according to offset bits addition and program counter value. Scheme may be applied during cache fill or dead cycle when taken branch is read from pipelined cache.
Preferably, all branches are translated into jump-instruction format by changing offset field of all branch instructions into an index field, and setting flag bit that accompanies the instruction to signify whether target calculation is complete. Such approach may avoid taken branch penalty, in many cases, leaving a penalty only when index calculation results in target of the branch residing in page adjacent to branch itself.


REFERENCES:
patent: 5485587 (1996-01-01), Matsuo et al.
patent: 5826053 (1998-10-01), Witt
patent: 5954816 (1999-09-01), Tran et al.
patent: 5974260 (1999-10-01), Gotou
patent: 5978906 (1999-11-01), Tran
patent: 6108774 (2000-08-01), Muthusamy
patent: 6115792 (2000-09-01), Tran
patent: 6266755 (2001-07-01), Yeager
patent: 6336178 (2002-01-01), Favor
patent: 6609194 (2003-08-01), Henry et al.

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