Combined multiplier and accumulator

Details Combined multiplier and accumulator Combined multiplier and accumulator

1994-11-28

1995-08-15

Envall, Jr., Roy N.

Boots, shoes, and leggings

364757, 364759, G06F 752

Patent

active

054425794

ABSTRACT:
A method for summing a sequence of binary product terms utilizing a modified Booth's algorithm in an arithmetic unit, wherein the arithmetic unit has a multiplicand register, a multiplier register, a data bus coupled to the multiplicand register and to the multiplier register, a pad bit located adjacent to the least signficant bit of the multiplier register, and an adder register coupled to the multiplicand register. After initializing the adder register, the values of the pad bit and the two least significant bits of the multiplier register are examined and a modified Booth's algorithm is performed on the data in the multiplicand register based on the examined values. The multiplier value is then shifted 2 places to the right, through the pad bit, and the multiplicand value is shifted 2 places to the left. The values of the pad bit and the two least significant bits of the multiplier register are again examined and a modified Booth's algorithm is performed on the data in the multiplicand register based on the shifted examined values.

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