Robert C. Valentine

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Method and apparatus for caching trace segments with multiple en

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent

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Method and apparatus for identifying potential entry points into

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent

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Method and apparatus for predicting when load instructions can b

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or...
Patent

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Method for encoding an instruction set with a load with...

Electrical computers and digital processing systems: processing – Processing control – Processing control for data transfer
Reexamination Certificate

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Method for optimized representation of page table entries

Electrical computers and digital processing systems: memory – Address formation – Varying address bit-length or size
Reexamination Certificate

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Profile ID: LFUS-PAI-P-1081309

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