Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or...
Patent
1997-11-25
1999-11-16
Maung, Zarni
Electrical computers and digital processing systems: processing
Dynamic instruction dependency checking, monitoring or...
712217, 712218, 712219, 712233, 712241, G06F 9312
Patent
active
059875950
ABSTRACT:
The invention in several embodiments includes an apparatus and a method for predicting whether store instructions can be safely executed out-of-order. The apparatus, includes at least one execution unit, a reorder buffer adapted to holding a plurality of instructions from an instruction sequence for execution by the execution units, and a memory storage device adapted to holding a collision history table. The collision history table has entries for load instructions of the instruction sequence Each of the entries is adapted to predicting when the associated load instruction is colliding.
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Ronen Ronny
Valentine Robert C.
Yoaz Adi
Intel Corporation
Maung Zarni
Najjar Saleh
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