Method and apparatus for caching trace segments with multiple en

Details Method and apparatus for caching trace segments with multiple en Method and apparatus for caching trace segments with multiple en

1997-12-01

2000-06-06

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

712238, G06F 1208

Patent

active

06073213&

ABSTRACT:
An apparatus includes a data array and control logic. The control logic is coupled to the data array and adapted to store at least one trace segment of instructions into the data array. The control logic allows the instructions of the trace segment to be sequentially retrieved beginning with a selected instruction. The selected instruction is offset from the first instruction of the trace segment. A method for caching instructions includes storing a first plurality of instructions in a first trace segment. A selected instruction of the first plurality of instructions is identified within the first trace segment. The selected instruction is offset from the first instruction of the first trace segment. The offset information related to the position of the selected instruction within the first trace segment is stored. A method for retrieving cached instructions, wherein the cached instructions are stored in a trace segment and the trace segment has a head instruction, includes determining a linear address related to a selected instruction to be retrieved. An entry point into the trace segment corresponding to the linear address is identified. The entry point is offset from the head instruction. The selected instruction is retrieved from the entry point within the identified trace segment.

REFERENCES:
patent: 5381533 (1995-01-01), Peleg et al.
patent: 5790822 (1998-08-01), Sheaffer et al.
Rotenberg et al., "Trace Cache: a Low Latency Approach to High Bandwidth Instruction Fetching", Microarchitecture, 1996, p. 24-34.
Intrater et al., "Performance Evaluation of a Decoded Instruction Cache for Variable Instruction-Length Computers", ACM, 1992, p. 106-113.

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