Method and apparatus for identifying potential entry points into

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories

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712238, G06F 1208

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active

06076144&

ABSTRACT:
An apparatus includes a data array, control logic, an entry candidate table, and a future target table. The control logic is coupled to the data array and adapted to store at least one trace segment of instructions into the data array. The entry candidate table is coupled to the control logic and is adapted to store offset information related to the position of a selected instruction within the trace segment. The future target table is coupled to the control logic and adapted to store a potential entry point into the trace segment. A method for caching instructions includes storing a first plurality of instructions in a first trace segment. A control flow instruction is identified from the first plurality of instructions and the outcome of the control flow instruction is predicted. The control flow instruction has a predicted taken target address and a predicted not-taken target address corresponding to the outcome predicted. The predicted not-taken target address is stored.

REFERENCES:
patent: 5381533 (1995-01-01), Peleg et al.
patent: 5790822 (1998-08-01), Sheaffer et al.
Intrater et al., "Performance Evaluation of a Decoded Instruction Cache for Variable Instruction-Length Computers," 1992, p 106-113, ACM.
Rotenberg et al., "Trace Cache: a Low Latency Approach to High Bandwidth Instruction Fetching," 1996, p 24-34, IEEE.

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