Electrical computers and digital processing systems: memory – Address formation – Varying address bit-length or size
Reexamination Certificate
2000-04-07
2003-11-11
Bataille, Pierre-Michel (Department: 2186)
Electrical computers and digital processing systems: memory
Address formation
Varying address bit-length or size
C711S201000, C711S208000, C711S219000
Reexamination Certificate
active
06647482
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to methods and system for memory management in general, and to methods and systems for managing memory in pages, in particular.
BACKGROUND OF THE INVENTION
Intermediate storage elements are known in the art. A conventional computer system includes random access memory (RAM), which is used for uploading software objects, executing them and for storing data objects, used by the software objects.
The RAM size is often limited. When the memory requirements exceed the RAM size, then the system can allocate a storage area on another storage element, such as a hard drive, and define this storage area as virtual memory, serving as an extension of the RAM. Data portions, which are not often used, can be stored in the virtual memory until the system retrieves them for further processing.
The RAM of a conventional computer system can be in the range of 32 MB-2 GB and the numbers increase constantly. It will be appreciated by those skilled in the art that the small data segments (a single bit, a byte and a word) can not be used for allocating memory in an efficient way. Conventional methods for managing memory allocate large portions of these segments. These portions are in the range of several kilobytes to several megabytes.
One conventional method, known in the art, for managing memory resources is called paged memory. This method determines a plurality of memory portions, called memory pages. Each memory page is of a predetermined set of sizes (for example, 4 KB, 16 KB). The memory is managed by a memory management module within the computer system, which can be implemented either in hardware or in software, either as a part of the operating system or of the computer chip-set.
The memory management module receives a memory allocation request for a block of memory, from a software module. The memory management module allocates memory pages having a total size, which can contain the requested amount of memory.
For each allocated memory portion, the memory allocator provides both a physical location and a logical representation. The physical location includes a selected portion of the overall memory size available in the computer system. The logical representation is the address seen by the software module. This address is used to index an entry in a special table, called the page table, which points to the physical location. It is noted that additional management mechanisms can be added to this structure, but those mechanisms will not be discussed herein below, so as to maintain the simplicity of the description.
The entries in the page table are called page table entries. Page table entries should indicate the physical address of the page, the page size and additional attributes about the page. The page size is always a power of 2, and the page address is always aligned on a page boundary (that is, can be divided by the page size). A page record is adapted to the environment in which it is processed. In a sixty-four-bit processor, this record includes, sixty-four bits and so does the entire address space. In an example, where the size of a memory page block is 4 KB (2
12
), fifty-two bits are required to point to any such block. In a system, which utilizes memory pages in several sizes, the page record has to include additional information relating to the size of the page associated with that record. The remaining bits in the record are used for various attributes such as, “read only”, “modified”, “write once”, “for system use only” and the like.
Reference is now made to
FIGS. 1A and 1B
.
FIG. 1A
is a representation of a page table entry string, generally referenced
10
, representing a predetermined page, which is known in the art.
FIG. 1B
is a representation of the memory page record string of
FIG. 1A
, representing a different memory page.
With reference to
FIG. 1A
, string
10
is divided into sub strings
12
,
14
and
16
. Sub-string
12
is a representation of the page address, sub-string
14
is a representation of the page size and sub-string
16
is a representation of the memory page attributes.
In the present example, the overall length of string
10
is sixty four bits, the length of page address sub-string
12
is fifty two bits, and the page size representation sub-string
14
includes three bits, which provide up to eight options of page sizes (2
3
). In the present example, the system utilizes the following page sizes: 4 KB, 8 KB, 16 KB, 32 KB, 64 KB, 128 KB, 256 KB and 512 KB. As a result of the above, the length which is set for the attribute sub-string is nine bits. It is noted that the system can utilize page sizes, which are not sequential, such as 4 KB, 32 KB, 64 KB, 256 KB, and the like.
Page size representation sub-string
14
stores a sequence “000” which, in the present example, indicates the first and smallest page size of 4 KB. With reference to
FIG. 1B
, the page size representation sub-string
14
stores a sequence “010” which, in the present example, indicates the third page size of 16 KB.
According to the above arrangement, the length of the attribute representation sub-string is the result of subtraction of the address sub-string and the size sub-string from the overall length of the page record string.
The above arrangement is also limited to eight different sizes of pages. If the system utilizes a greater number of pages, then additional bits have to be allocated from the attribute sub-string to the page size sub-string, thus reducing even more the length of the attribute sub-string.
SUMMARY OF THE PRESENT INVENTION
A method for optimized representation of page table entries and corresponding page-based memory access scheme are disclosed. The method includes the use of a predetermined length memory page pointer record that implements a separator bit between variable-length page address and page size sub-strings. Based on the location of the separator bit, the page sized used by a memory system may be determined. Similarly, a page size to be used by the memory system may be defined by generating memory page pointer records that have a separator bit at a location corresponding to the desired page size. The memory page pointer record may also include attribute bits that define characteristics of the memory stored at a given page and offset specified by the record. The method and scheme also support the use of multiple page sizes within the same memory system.
REFERENCES:
patent: 4897652 (1990-01-01), Leon
patent: 5465337 (1995-11-01), Kong
patent: 5648774 (1997-07-01), Hsieh
patent: 5761741 (1998-06-01), Robbins et al.
patent: 5907867 (1999-05-01), Shinbo et al.
patent: 6088780 (2000-07-01), Yamada et al.
Bach Maury J.
Glew Andrew F.
Kahn Opher D.
Ronen Ronny
Uhlig Richard A.
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