Electrical computers and digital processing systems: processing – Processing control – Processing control for data transfer
Reexamination Certificate
2001-02-06
2004-04-20
Kim, Kenneth S. (Department: 2183)
Electrical computers and digital processing systems: processing
Processing control
Processing control for data transfer
C712S023000, C712S226000, C712S244000
Reexamination Certificate
active
06725362
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to processor architectures and instruction sets, and in particular, to processor architectures with instruction sets that provide load with conditional fault instructions.
BACKGROUND
In modern processors, for example, a Central Processing Unit (CPU), execution of instructions occurs, in general, in the following sequential order: the CPU reads an instruction, the CPU decodes the instruction, and, then, the CPU executes the instruction. In older CPUs the clock speed of the processor was generally slow enough that the reading, decoding and executing of each instruction could occur in a single clock cycle. However, modern microprocessors have improved performance by going to shorter clock cycles (that is, higher frequencies). These shorter clock cycles tend to make instructions require multiple smaller sub-actions which can fit into the cycle time. Executing many such sub-actions in parallel, as in a pipelined and/or superscalar processor, can improve performance even further. For example, to execute the decoding portion of a simple multiplication instruction involves several steps, including: obtaining a first operand from the instruction, moving the first operand to an appropriate storage location, obtaining a second operand, multiplying the first and second operands, and storing the result in a result storage location. Included in these instruction steps are load operations, which can access the memory to obtain the operand(s) from a source memory location or register and then either store the operand(s) or the result of the multiplication operation into a destination register or registers, depending on the implementation. Unfortunately, the cycle time of microprocessor technology has decreased much more rapidly than that of off-die memory technology, hence load instructions/operations are experiencing long latency periods, which adversely affect processor efficiency and performance.
Therefore, what is needed is a method for providing early, that is, out-of-order, execution of load operations, as specified in an instruction, to obtain the necessary data before the data is needed for the execution of the instruction without causing unwarranted fault conditions.
REFERENCES:
patent: 5712997 (1998-01-01), Dice
Kahn Opher D.
Valentine Robert C.
Intel Corporation
Kenyon & Kenyon
Kim Kenneth S.
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