Electronic digital logic circuitry
With test facilitating feature
Inventor
active
I/O driver design for simultaneous switching noise minimization
Method for forming minimum area structures for sub-micron CMOS E
Microelectronic circuit including silicided field-effect transis
Switchable pull-ups and pull-downs for IDDQ testing of integrate
Switchable pull-ups and pull-downs for IDDQ testing of integrate
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