Switchable pull-ups and pull-downs for IDDQ testing of integrate

Details Switchable pull-ups and pull-downs for IDDQ testing of integrate Switchable pull-ups and pull-downs for IDDQ testing of integrate

1995-09-26

1997-09-23

Karlsen, Ernest F.

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

324763, 371 223, G01R 3128

Patent

active

056708904

ABSTRACT:
An integrated circuit includes a plurality of signal lines, a plurality of pull transistors connected between the signal lines respectively and an electrical potential, and an IDDQ test control for turning on the pull transistors for normal operation, and for turning off the pull transistors for IDDQ testing. The IDDQ test control includes a test signal generator for generating an IDDQ test control signal that turns off the pull transistors, and an IDDQ test signal line that is connected to the test signal generator and to the pull transistors. The pull transistors are designed within a periphery of the circuit, and the IDDQ test signal line forms a ring. The test signal generator includes an external pin, a special buffer, or a boundary scan system including a chain of boundary scan cells and a test access port controller. The test control signal can be generated by one of the boundary scan cells, or by the test access port controller.

REFERENCES:
patent: 5097206 (1992-03-01), Perner
patent: 5321354 (1994-06-01), Ooshima et al.
patent: 5371457 (1994-12-01), Lipp
patent: 5467026 (1995-11-01), Arnold

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