Method for forming minimum area structures for sub-micron CMOS E

Details Method for forming minimum area structures for sub-micron CMOS E Method for forming minimum area structures for sub-micron CMOS E

1996-07-19

1998-03-17

Trinh, Michael

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438133, 438202, 438228, H01L 218238

Patent

active

057286124

ABSTRACT:
A method and resulting structure is disclosed for extending or enlarging the effective volumes of one or more source, drain, and/or emitter regions of integrated circuit structures such as an SCR structure and/or an MOS structure designed to protect an integrated circuit structure from damage due to electrostatic discharge (ESD). The additional effective volume allows the SCR and/or MOS protection devices to handle additional energy from an electrostatic discharge applied, for example, to I/O contacts electrically connected to the SCR protection structure. The additional effective volume is obtained, without additional doping or masking steps, by forming individual deep doped regions or wells, beneath one or more heavily doped source, drain, and emitter regions, at the same time and to the same depth and doping concentration as conventional main P wells and/or N wells which are simultaneously formed in the substrate, whereby no additional masks and implanting steps are needed.

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