4. Error detection/correction and fault detection/recovery
  5. Pulse or data error handling
  6. Digital data error correction

Luis A. Lastras-Montano

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Error control coding methods for memories with subline accesses

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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High availability memory system

Electrical computers and digital processing systems: memory – Addressing combined with specific memory configuration or... – For multiple memory modules
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Iterative write pausing techniques to improve read latency...

Static information storage and retrieval – Systems using particular element – Amorphous
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Low latency constrained coding for parallel busses

Coded data generation or conversion – Digital code to digital code converters – To or from mixed base codes
Reexamination Certificate

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System and method for error correction and detection in a...

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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Profile ID: LFUS-PAI-P-2159850

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