Coded data generation or conversion – Digital code to digital code converters – To or from mixed base codes
Reexamination Certificate
2007-08-29
2008-12-30
Mai, Lam T (Department: 2819)
Coded data generation or conversion
Digital code to digital code converters
To or from mixed base codes
C341S050000
Reexamination Certificate
active
07471219
ABSTRACT:
A system and method for providing low latency constrained coding for parallel busses. The method includes receiving a value for a number of transfers and a number of possible constrained patterns between adjacent transfer rows. Data to be encoded is received. The data is converted into indices of constrained patterns, the converting including a number base change into a new base. The new base is chosen so as to optimize the number of operations required to perform the converting subject to the new base being at least as large as the number of possible constrained patterns between adjacent transfer rows. The indices of the constrained pattern are converted into encoded data. The encoded data is then output.
REFERENCES:
patent: 5513135 (1996-04-01), Dell et al.
patent: 5572736 (1996-11-01), Curran
patent: 5874833 (1999-02-01), Perry et al.
patent: 6252956 (2001-06-01), Karino
patent: 6381685 (2002-04-01), Dell et al.
patent: 6701404 (2004-03-01), Hamre et al.
patent: 6732214 (2004-05-01), Cohen et al.
patent: 6763406 (2004-07-01), Devanney et al.
patent: 6834335 (2004-12-01), Fallah et al.
patent: 6933863 (2005-08-01), Visalli et al.
patent: 7043670 (2006-05-01), Alani et al.
patent: 7139852 (2006-11-01), LaBerge
patent: 7205815 (2007-04-01), Park
patent: 7296091 (2007-11-01), Dutta et al.
patent: 2007/0005282 (2007-01-01), Messier
patent: 0186385 (1986-07-01), None
patent: 2001274846 (2001-10-01), None
Brhambatt, et al. “Adaptive Low-Power Bus Encoding Based On Weighted Code Mapping”. IEEE 0-7803-9390-2/06 ISCAS. Feb. 2006. pp. 1739-1742.
Stan, et al. “Bus-Invert Coding for Low-Power I/O”. IEEE Transactions on Very Large Scale Integration. vol. 3, No. 1. Mar. 1995. pp. 49-58.
Campello, et al. “Constrained Systems With Unconstrained Positions”. IEEE Transactions on Information Theory. vol. 48, No. 4. Apr. 2002. pp. 866-879.
Sotiriadis, et al. “Energy Reduction in VLSI Computation Modules: An Information Theoretic Approach”. IEEE Transactions on Information Theory. vol. 49, No. 4. Apr. 2003. pp. 790-808.
Cover, Thomas M. “Enumerative Source Encoding”. IEE Transactions on Information Theory. vol. IT-19 No. 1. Jan. 1973. pp. 73-77.
Poo, et al. “Tradeoff Functions For Constrained Systems With Unconstrained Positions”. IEEE Transactions on Information Theory. vol. 52, No. 4. Apr. 2006. pp. 1425-1449.
Babvey, Sharareh. “Delay and Power Reduction in Deep Submicron Buses”. Georgia State University. May 2005.67 pgs.
van Wijngaarden, et al. “Maximum Runglength-Limited Codes with Error Control Capabilities”. IEEE Journal on Selected Areas in Communications. vol. 19, No. 4. Apr. 2001. pp. 602-611.
Cheng, et al. “Memory Bus Encoding for Low Power: A Tutorial”. IEEE 0-7695-1025-6-01. Jun. 2001. pp. 199-204.
Augspurger Lynn
Cantor & Colburn LLP
International Business Machines - Corporation
Mai Lam T
LandOfFree
Low latency constrained coding for parallel busses does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Low latency constrained coding for parallel busses, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Low latency constrained coding for parallel busses will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4028748