High availability memory system

Details High availability memory system High availability memory system

2009-02-23

2011-12-27

Peugh, Brian (Department: 2187)

Electrical computers and digital processing systems: memory

Addressing combined with specific memory configuration or...

For multiple memory modules

Reexamination Certificate

active

08086783

ABSTRACT:
A memory system with high availability is provided. The memory system includes multiple memory channels. Each memory channel includes at least one memory module with memory devices organized as partial ranks coupled to memory device bus segments. Each partial rank includes a subset of the memory devices accessible as a subchannel on a subset of the memory device bus segments. The memory system also includes a memory controller in communication with the multiple memory channels. The memory controller distributes an access request across the memory channels to access a full rank. The full rank includes at least two of the partial ranks on separate memory channels. Partial ranks on a common memory module can be concurrently accessed. The memory modules can use at least one checksum memory device as a dedicated checksum memory device or a shared checksum memory device between at least two of the concurrently accessible partial ranks.

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