4. Electrical computers and digital processing systems: memory
  5. Storage accessing and control
  6. Hierarchical memories

Ian W. Jones

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Apparatus and method for generating a partial fullness...

Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output data buffering
Reexamination Certificate

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Apparatus and method for sequencing memory operations in an...

Multiplex communications – Pathfinding or routing – Switching a message which includes an address header
Reexamination Certificate

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Asynchronous arbiter using multiple arbiter elements to enhance

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Asynchronous arbiter using multiple arbiter elements to enhance

Multiplex communications – Wide area network – Packet switching
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Asynchronous control circuit with symmetric forward and...

Multiplex communications – Miscellaneous
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Profile ID: LFUS-PAI-P-523270

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