Apparatus and method for sequencing memory operations in an...

Details Apparatus and method for sequencing memory operations in an... Apparatus and method for sequencing memory operations in an...

2005-04-19

2005-04-19

Ho, Duc (Department: 2665)

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

C370S394000, C711S105000, C340S002280

Reexamination Certificate

active

06882645

ABSTRACT:
One embodiment of the present invention provides a system that facilitates implementing a memory mechanism within an asynchronous switch fabric. The system includes a memory device, which does not preserve first-in, first-out semantics such as a random access memory or a stack. The system also includes a data destination horn, for routing data from a trunk line to a plurality of destinations. The memory device is one destination of the plurality of destinations. The system further includes a data source funnel, for routing data from a plurality of sources into the trunk line. The memory device is a source of the plurality of sources.

REFERENCES:
patent: 5278969 (1994-01-01), Pashan et al.
patent: 6192049 (2001-02-01), Sohraby
patent: 6466590 (2002-10-01), Park et al.

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