Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1997-05-15
1999-02-23
Shah, Alpesh M.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
395287, 395856, 711150, G06F 1300
Patent
active
058753397
ABSTRACT:
An arbiter circuit having a plurality of mutual exclusion (MUTEX) elements is disclosed. Each of the MUTEX elements is coupled to receive a different combination of request signals and their complements and grant signals and their complements fed back from the output of the arbiter circuit. At any point in time, only one of the plurality of MUTEX elements is selected based on the current state of the grant signals. The selected MUTEX element is used to arbitrate and grant one user exclusive access to a shared resource among the one or more users requesting exclusive access to the shared resource. All the other MUTEX elements in the arbiter circuit are disabled and are inactive during this time. After issuing the grant signal, the selected MUTEX element is disabled and a new MUTEX element responsible for issuing the next grant signal is selected based the new state of the grant signals.
REFERENCES:
patent: 4096569 (1978-06-01), Barlow
patent: 4423384 (1983-12-01), DeBock
patent: 4473880 (1984-09-01), Budde et al.
patent: 4604694 (1986-08-01), Hough
patent: 4641266 (1987-02-01), Walsh
patent: 4698753 (1987-10-01), Hubbins et al.
patent: 4774660 (1988-09-01), Conforti
patent: 4835672 (1989-05-01), Zenk et al.
patent: 4872004 (1989-10-01), Bahnick et al.
patent: 4894565 (1990-01-01), Marquardt
patent: 4924380 (1990-05-01), McKinney et al.
patent: 4956820 (1990-09-01), Hashimoto
patent: 4962379 (1990-10-01), Yasuda et al.
patent: 4969120 (1990-11-01), Azevedo et al.
patent: 5038274 (1991-08-01), Nielsen
patent: 5038276 (1991-08-01), Bozzetti et al.
patent: 5151994 (1992-09-01), Wille et al.
patent: 5167022 (1992-11-01), Bahr et al.
patent: 5193197 (1993-03-01), Thacker
patent: 5214775 (1993-05-01), Yabushita et al.
patent: 5263146 (1993-11-01), Mishima
patent: 5265212 (1993-11-01), Bruce, II
patent: 5313641 (1994-05-01), Simcoe et al.
patent: 5339443 (1994-08-01), Lockwood
patent: 5341052 (1994-08-01), Dike et al.
patent: 5404540 (1995-04-01), Dike
patent: 5408629 (1995-04-01), Tsuchiva et al.
patent: 5442758 (1995-08-01), Slingwine et al.
patent: 5454111 (1995-09-01), Frame et al.
Slides presented at the Proceedings of the VII Banff Workshop:Asynchronous Hardware Design, Aug. 28-Sep. 23, 1993, 3 Pages, by Al Davis, Hewlett Packard, Palo Alto, California.
Article entitled "Synthesizing Asynchronous Circuits:Practice & Experience", (from the book from the VII Banff Workshop: Asynchronous Hardware Design, held in 1993), by Al Davis, Department of Computer Science, University of Utah, 3 Pages, 1995.
"Introduction to VLSI Systems", Carver Mead et al., Oct. 1980, pp. 260-261.
Engineering notebook pages, dated Oct. 11 & 12, 1988, prepared by Mr. Ken Stevens while employed by H-P, in Palo Alto, CA. (Note, no citation is provided because to Applicants' knowledge, these pages were never published.).
"SBC: A Multiport Memory Building Block for Asynchronous Systems", by A.L. Davis & Ken Stevens, Schlumberger P.A. Research Center, Palo Alto, CA, Nov. 12, 1987. (Note, no citation is provided because to the Applicants' knowledge, this paper was never published.).
"2 Input Sequence Example", by Alex Yakovlev, Apr. 30, 1994. This reference was obtained from an asynchronous systems interest group email circulation. It is believed that additional copies may be obtained by contacting Mr. Yakovlev at email ID alex.yakovlev@newcastle.ac.uk.
"Introduction to VLSI Systems", Carver Mead and Lynn Conway, Addison-Wesley, 1980, pp. 260-261.
Jones Ian W.
Molnar Charles E.
Rose James W.
Shah Alpesh M.
Sun Microsystems Inc.
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