Asynchronous control circuit with symmetric forward and...

Multiplex communications – Miscellaneous

Reexamination Certificate

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C326S093000, C713S400000

Reexamination Certificate

active

07436861

ABSTRACT:
One embodiment of the present invention provides a control queue for an asynchronous circuit that includes a number of control modules coupled together linearly to form the control queue. These control modules include a prior module, a present module, and a next module. The present module is configured to receive one or more forward-going inputs from the prior module and one or more reverse-going inputs from the next module. The present module asynchronously generates one or more forward-going outputs to the next module and one or more reverse-going outputs to the prior module. The modules within the control queue are constructed so that the latency of the forward-going signals through the control queue is equal to the latency of the reverse-going signals through the control queue.

REFERENCES:
patent: 5386585 (1995-01-01), Traylor
patent: 6356117 (2002-03-01), Sutherland et al.
patent: 6700410 (2004-03-01), Ebergen
patent: 6958627 (2005-10-01), Singh et al.
Publication entitled “GasP: A Minimal FIFO Control,” by Ivan Sutherland and Scott Fairbanks, 2001 IEEE, Proceedings of Seventh International Symposium on Advanced Research in Asynchronous Circuits and Systems, pp. 46-53.

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