4. Static information storage and retrieval
  5. Floating gate
  6. Particular connection

Fabiano Fontana

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Array cell circuit with split read/write line

Static information storage and retrieval – Floating gate – Particular connection
Patent

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CMOS logic gate clamping circuit

Electronic digital logic circuitry – Accelerating switching
Patent

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Enhanced CPLD macrocell module having selectable bypass of...

Electronic digital logic circuitry – Multifunctional or programmable – Array
Reexamination Certificate

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Enhanced CPLD macrocell module having selectable bypass of...

Electronic digital logic circuitry – Multifunctional or programmable – Array
Reexamination Certificate

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Enhanced method of testing semiconductor devices having nonvolat

Static information storage and retrieval – Read/write circuit – Testing
Patent

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Profile ID: LFUS-PAI-P-142236

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