Static information storage and retrieval – Read/write circuit – Testing
Patent
1998-03-23
1999-11-09
Nelms, David
Static information storage and retrieval
Read/write circuit
Testing
365200, G11C 700
Patent
active
059826835
ABSTRACT:
An enhanced method of testing semiconductor devices having nonvolatile elements by determining regions of the semiconductor having differing orders of probability that a defect will occur. The enhanced method of testing includes testing of regions from the highest probability to the lowest probability of having a defect. Nonvolatile memory elements in the region being tested are placed in a high impedance state, bypass circuits in the region being tested are activated to bypass the nonvolatile memory elements that control the state of elements in the region being tested and test vectors are applied to the elements that are controlled by the bypassed nonvolatile memory elements. This procedure is repeated for the next untested region having the highest probability of having a defect until all regions have been tested.
REFERENCES:
patent: 5113399 (1992-05-01), Woods et al.
patent: 5343434 (1994-08-01), Noguchi
patent: 5357521 (1994-10-01), Cheng et al.
patent: 5514975 (1996-05-01), Sartwell et al.
patent: 5623215 (1997-04-01), Maytum
patent: 5631912 (1997-05-01), Mote, Jr.
patent: 5748640 (1998-05-01), Jiang et al.
Choi Steve
Chui Jenny
Fontana Fabiano
Lau Benjamin
Watson James A.
Advanced Micro Devices , Inc.
Auduong Gene N.
Nelms David
Nelson H. Donald
LandOfFree
Enhanced method of testing semiconductor devices having nonvolat does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Enhanced method of testing semiconductor devices having nonvolat, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Enhanced method of testing semiconductor devices having nonvolat will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1465318