Electronic digital logic circuitry – Multifunctional or programmable – Array
Reexamination Certificate
2002-08-13
2003-11-18
Tan, Vibol (Department: 2819)
Electronic digital logic circuitry
Multifunctional or programmable
Array
C326S039000
Reexamination Certificate
active
06650142
ABSTRACT:
FIELD OF DISCLOSURE
The present disclosure of invention relates generally to monolithic integrated circuits, and more specifically to a repeated macrocell module design for use within Programmable Logic Devices (PLD's).
The disclosure relates even more specifically to a macrocell module design as applied to a subclass of PLD's known as Complex Programmable Logic Devices (CPLD's) and High-Density Complex Programmable Logic Devices (HCPLD's).
After this disclosure is lawfully published, the owner of the present patent application has no objection to the reproduction by others of textual and graphic materials contained herein provided such reproduction is for the limited purpose of understanding the present disclosure of invention and of thereby promoting the useful arts and sciences. The owner does not however disclaim any other rights that may be lawfully associated with the disclosed materials, including but not limited to, copyrights in any computer program listings or art works or other works provided herein, and to trademark or trade dress rights that may be associated with coined terms or art works provided herein and to other otherwise-protectable subject matter included herein or otherwise derivable herefrom.
If any disclosures are incorporated herein by reference and such incorporated disclosures conflict in part or whole with the present disclosure, then to the extent of conflict, and/or broader disclosure, and/or broader definition of terms, the present disclosure controls. If such incorporated disclosures conflict in part or whole with one another, then to the extent of conflict, the later-dated disclosure controls.
DESCRIPTION OF RELATED ART
Field-Programmable Logic Devices (FPLD's) have continuously evolved to better serve the unique needs of different end-users. From the time of introduction of simple PLD's such as the Advanced Micro Devices 22V10™ Programmable Array Logic device (PAL), the art has branched out in several different directions.
One evolutionary branch of FPLD's has branched out along a paradigm known as Complex PLD's or CPLD's. This paradigm is characterized by devices such as the ispMACH™ family (available from Lattice Semiconductor Corp. of Oregon). Examples of CPLD circuitry are seen in U.S. Pat. No. 5,015,884 (issued May 14, 1991 to Om P. Agrawal et al.) and U.S. Pat. No. 5,151,623 (issued Sep. 29, 1992 to Om P. Agrawal et al.) as well as in other CPLD patents cited above, including U.S. Pat. No. 6,150,841 which will be specifically addressed herein.
A CPLD device may be characterized as being constituted by a monolithic, integrated circuit (IC) that typically has four major features as follows.
(1) A user-accessible, configuration-defining memory means, such as EPROM, EEPROM, anti-fused, fused, SRAM, or other, is provided in the CPLD device so as to be at least once-programmable by device users for defining user-provided configuration instructions. Static Random Access Memory or SRAM is of course, a form of reprogrammable memory that can be differently programmed many times. Electrically Erasable and reProgrammable ROM or EEPROM is an example of nonvolatile reprogrammable memory. The configuration-defining memory of a CPLD device can be formed of a mixture of different kinds of memory elements if desired (e.g., SRAM and EEPROM). Typically it is of the nonvolatile, In-System reProgrammable (ISP) kind such as EEPROM.
(2) Input/Output means (IO's) are provided for interconnecting internal circuit components of the CPLD device with external circuitry. The IO's may have fixed configurations or they may include configurable features such as variable slew-output drivers whose characteristics may be fine tuned in accordance with user-provided configuration instructions stored in the configuration-defining memory means.
(3) Programmable Logic Blocks (PLB's) are provided for carrying out user-programmed logic functions as defined by user-provided configuration instructions stored in the configuration-defining memory means. Typically, each of the many PLB's of a CPLD has at least a Boolean sum-of-products generating circuit (e.g., an AND/OR array or an equivalent such as a NAND/NAND array) or a Boolean product-of-sums generating circuit (e.g., an OR/AND array or an equivalent such as a NOR/NOR array) that is user-configurable to define a desired Boolean function, —to the extent allowed by the number of product terms (PT's) or sum terms (ST's) that are combinable by that circuit.
Each PLB may have other resources such as input signal pre-processing resources and output signal post-processing resources. The output signal post-processing resources may include result storing and/or timing adjustment resources such as clock-synchronized registers. Although the term ‘PLB’ was adopted by early pioneers of CPLD technology, it is not uncommon to see other names being given to the repeated portion of the CPLD that carries out user-programmed logic functions and timing adjustments to the resultant function
(4) An interconnect network is generally provided for carrying signal traffic within the CPLD between various PLB's and/or between various IO's and/or between various IO's and PLB's. At least part of the interconnect network is typically user-configurable so as to allow for programmably-defined routing of signals between various PLB's and/or IO's in accordance with user-defined routing instructions stored in the configuration-defining memory means.
In contrast to FPGA's, which are LUT-based PLD's (where a LUT in this context is a user-programmable Look-Up Table), gate-based CPLD's are generally recognized in the art as having a comparatively less-expansive capability of implementing a wide variety of functions, in other words, not being able to implement all Boolean functions for a given input space as can a LUT. CPLD's however, are expected to provide their lesser variety of logic functions with comparatively higher throughput speeds (smaller signal-propagation delays). In other words, wide functionality is sacrificed to obtain shorter, pin-to-pin signal delays. Thus pin-to-pin delay is an important measure of CPLD performance. Also, because length of signal routings through the programmable interconnect of a CPLD is often arranged so it will not vary significantly despite different signal routings, CPLD's are generally recognized as being able to provide relatively consistent signal delays whose values often do not vary substantially in spite of how the corresponding CPLD configuring software (the partitioning, placement and routing software which configures the CPLD) behaves. Many devices in the Lattice/Vantis ispMACH™ family provide such a consistent signal delay characteristic under the trade name of SpeedLocking™. The more generic term, Speed-Consistency will be used interchangeably herein with the term, SpeedLocking™.
A newly evolving sub-branch of the growing families of CPLD devices is known as High-Density Complex Programmable Logic Devices (HCPLD's). This sub-branch may be generally characterized as being constituted by monolithic IC's that each have large numbers of I/O terminals (e.g., Input/Output pins) in the range of about 32 or more (e.g., 64, 96, 128, 192, 256, 320, etc.) and/or have large numbers of result-storing macrocell units in the range of about 32 or more (e.g., 64, 128, 256, 320, 512, 1024, etc.). The process of concentrating large numbers of I/O pins and/or large numbers of macrocells into a single CPLD device raises new challenges for achieving relatively broad functionality, high speed, and Speed-Consistency (SpeedLocking™) in the face of wide varieties of configuration software.
More detailed discussion regarding different HCPLD architectures (1, 2, or 3 level hierarchical interconnects) and interrelated topics (e.g., adaptability to configuration software) are provided in the above-cited U.S. Pat. No. 6,184,713. As such they will not be repeated here except to briefly note the following. Confi
Agrawal Om P.
Bosco Gilles M.
Fontana Fabiano
Gimlan Gideon
Lattice Semiconductor Corporation
MacPherson Kwok & Chen & Heid LLP
Tan Vibol
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