4. Semiconductor device manufacturing: process
  5. Making field effect device having pair of active regions...
  6. Having insulated gate

Anton P. Eppich

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6F 2 DRAM cell design with 3F-pitch folded digitline sense...

Static information storage and retrieval – Interconnection arrangements
Reexamination Certificate

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Dram cell design with folded digitline architecture and...

Static information storage and retrieval – Interconnection arrangements
Reexamination Certificate

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Memory array with overlapping buried digit line and active...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate

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Memory cell with buried digit line

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate

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Memory cell, array, device and system with overlapping...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate

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Profile ID: LFUS-PAI-P-2290972

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