Memory cell, array, device and system with overlapping...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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Details

C257S300000, C257S301000, C257S302000, C257S303000, C257S304000, C257S305000, C257S306000, C257S296000, C257S311000

Reexamination Certificate

active

07042047

ABSTRACT:
A memory cell, array and device include an active area formed in the substrate with a vertical transistor including a first end disposed over a first portion of the active area. The vertical transistor is formed as an epitaxial post on the substrate surface, extends from the surface of the substrate, and includes a gate formed around a perimeter of the epitaxial post. A capacitor is formed on the vertical transistor and a buried digit line vertically couples to a second portion of the active area. An electronic system and method for forming a memory cell are also disclosed.

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patent: 2005/0104107 (2005-05-01), Fazan et al.

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