Memory array with overlapping buried digit line and active...

Details Memory array with overlapping buried digit line and active... Memory array with overlapping buried digit line and active...

2007-09-18

2007-09-18

Sarkar, Asok K. (Department: 2891)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S268000, C438S689000, C257SE21660

Reexamination Certificate

active

11196583

ABSTRACT:
A memory cell, array and device include an active area formed in a substrate with a vertical transistor including a first end disposed over a first portion of the active area. The vertical transistor is formed as an epitaxial post on the substrate surface, extends from the surface of the substrate, and includes a gate formed around a perimeter of the epitaxial post. A capacitor is formed on the vertical transistor and a buried digit line vertically couples to a second portion of the active area. An electronic system and method for forming a memory cell are also disclosed.

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