Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2008-01-14
2009-02-24
Pert, Evan (Department: 2826)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S201000, C438S257000, C438S260000, C438S593000
Reexamination Certificate
active
07494861
ABSTRACT:
MOSFET devices suitable for operation at gate lengths less than about 40 nm, and methods of their fabrication is being presented. The MOSFET devices include a ground plane formed of a monocrystalline Si based material. A Si based body layer is epitaxially disposed over the ground plane. The body layer is doped with impurities of opposite type than the ground plane. The gate has a metal with a mid-gap workfunction directly contacting a gate insulator layer. The gate is patterned to a length of less than about 40 nm, and possibly less than 20 nm. The source and the drain of the MOSFET are doped with the same type of dopant as the body layer. In CMOS embodiments of the invention the metal in the gate of the NMOS and the PMOS devices may be the same metal.
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Chu Jack Oon
Doris Bruce B.
Ieong Meikei
Wang Jing
International Business Machines - Corporation
Pert Evan
Sai-Halasz George
Trepp Robert M.
Wilson Scott R
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