Timing failure remedying apparatus for an integrated...

Details Timing failure remedying apparatus for an integrated... Timing failure remedying apparatus for an integrated...

2007-08-22

2009-10-13

Ton, David (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S718000, C714S733000, C714S738000, C714S744000

Reexamination Certificate

active

07603600

ABSTRACT:
A timing failure remedying apparatus for an integrated circuit has a comparator which compares a value captured in a taking-out scan chain for reference through an operation of a processing core for reference according to a first clock signal with a value captured in a taking-out scan chain to be tested through an operation of a processing core to be tested according to a second clock signal, a diagnosing unit which determines a timing failure in the logic circuit to be tested on the basis of a result of comparison by the comparator, and an adjuster which adjusts at least either a second cycle or a delay amount of the second clock signal. It is possible to examine a position of the timing failure or the number of the timing failures in the integrated circuit diagnosed as that its logic is normal but the timing failure occurs therein.

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patent: 7539598 (2009-05-01), Jang et al.
patent: 2007/0186132 (2007-08-01), Dingemanse
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patent: 2001-43261 (2001-02-01), None
patent: 2003-4807 (2003-01-01), None

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