Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2007-01-16
2007-01-16
Smith, Matthew S. (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S300000, C438S481000, C438S607000, C257S347000
Reexamination Certificate
active
09691353
ABSTRACT:
A double gated silicon-on-insulator (SOI) MOSFET is fabricated by forming epitaxially grown channels, followed by a damascene gate. The double gated MOSFET features narrow channels, which increases current drive per layout width and provides low out conductance.
REFERENCES:
patent: 4996574 (1991-02-01), Shirasaki
patent: 5273921 (1993-12-01), Neudeck et al.
patent: 5273929 (1993-12-01), Hirtz et al.
patent: 5294564 (1994-03-01), Karapiperis et al.
patent: 5336633 (1994-08-01), Tsuruta
patent: 5365097 (1994-11-01), Kenney
patent: 5545586 (1996-08-01), Koh
patent: 6040605 (2000-03-01), Sano et al.
patent: 6171937 (2001-01-01), Lustig
patent: 6441433 (2002-08-01), En et al.
patent: 6479847 (2002-11-01), Misewich et al.
patent: 6483156 (2002-11-01), Adkisson et al.
patent: 6563131 (2003-05-01), Adkisson et al.
patent: 6660596 (2003-12-01), Adkisson et al.
patent: 6833569 (2004-12-01), Dokumaci et al.
patent: 2002/0153587 (2002-10-01), Adkisson et al.
patent: 2003/0006410 (2003-01-01), Doyle
patent: 2005/0205932 (2005-09-01), Cohen
patent: 11-251579 (1999-09-01), None
Adkisson James W.
Agnello Paul D.
Ballantine Arne W.
Divakaruni Rama
Jones Erin C.
Canale Anthony
International Business Machines - Corporation
Nguyen Khiem
Smith Matthew S.
Whitham Curtis Christofferson & Cook PC
LandOfFree
Method of fabricating semiconductor side wall fin does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of fabricating semiconductor side wall fin, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of fabricating semiconductor side wall fin will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3820234