Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2007-07-03
2007-07-03
Lamarre, Guy (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S727000, C714S707000, C713S400000, C713S500000, C326S093000, C327S291000
Reexamination Certificate
active
10906407
ABSTRACT:
When testing an ASIC using functional clocks, a control circuit at the clock root incorporates additional test logic in the root and a deskewer for clock control, giving rise to a very flexible control that can pass clock signals at a number of clock rates and can pass only a single clock edge, thereby permitting the passage of the required number of clock pulses for a test. The system uses the functional clock and the clock distribution tree designed into the ASIC.
REFERENCES:
patent: 5256912 (1993-10-01), Rios
patent: 5438601 (1995-08-01), Maegawa et al.
patent: 5629946 (1997-05-01), Takano
patent: 5673271 (1997-09-01), Ohsawa
patent: 5809543 (1998-09-01), Byers et al.
patent: 6199185 (2001-03-01), Ju et al.
patent: 6223297 (2001-04-01), Inoue
patent: 6327667 (2001-12-01), Hetherington et al.
patent: 6327684 (2001-12-01), Nadeau-Dostie et al.
patent: 6338127 (2002-01-01), Manning
patent: 6404250 (2002-06-01), Volrath et al.
patent: 6442722 (2002-08-01), Nadeau-Dostie et al.
patent: 6449728 (2002-09-01), Bailey
patent: 6507230 (2003-01-01), Milton
patent: 6598192 (2003-07-01), McLaurin et al.
patent: 6724850 (2004-04-01), Hartwell
patent: 6877123 (2005-04-01), Johnston et al.
patent: 6966021 (2005-11-01), Rajski et al.
patent: 7007213 (2006-02-01), Wang et al.
patent: 2003/0084390 (2003-05-01), Tamarapalli et al.
patent: 2004/0163021 (2004-08-01), Nadeau-Dostie
patent: 2005/0166104 (2005-07-01), Rich et al.
patent: 2005/0240847 (2005-10-01), Nadeau-Dostie et al.
patent: 2005/0276321 (2005-12-01), Konuk
Farmer Henry R.
Grise Gary D.
Milton David W.
Taylor Mark R.
Harding W. Riyon
Lamarre Guy
Trimmings John P.
LandOfFree
Clock control circuit for test that facilitates an at speed... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Clock control circuit for test that facilitates an at speed..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Clock control circuit for test that facilitates an at speed... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3733447