Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2007-04-24
2007-04-24
Tu, Christine T. (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
72, 72
Reexamination Certificate
active
11140579
ABSTRACT:
A method for performing ATPG (automatic test pattern generation) and fault simulation in a scan-based integrated circuit, based on a selected clock order in a selected capture operation, in a selected scan-test mode or a selected self-test mode. The method comprises compiling704the RTL (register-transfer level) or Gate-Level HDL (hardware description language) code701based on the Input Constraints702and a Foundry Library703, into a Sequential Circuit Model705. The Sequential Circuit Model705is then transformed706into an equivalent Combinational Circuit Model707for performing Forward and/or Backward Clock Analysis708to determine the driving and observing clocks for all inputs and outputs of all combinational logic gates in the Combinational Circuit Model707. The analysis results are used for Uncontrollable/Unobservable Labeling709of selected inputs and outputs of the combinational logic gates. Finally, ATPG and/or Fault Simulation710are performed according to the Uncontrollable/Unobservable Labeling709to generate the HDL Test Benches and ATE Test Programs711.
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Lin et al, “Test Generation for Designs with Multiple Clocks,” Proc. ACM/IEEE Design Automation Conf., Anaheim, California, pp. 662-667, Jun. 2-6, 2003.
Abdel-Hafez Khader S.
Jiang Zhigang
Sheu Boryau (Jack)
Wang Laung-Terng (L.-T.)
Wang Zhigang
Syntest Technologies, Inc.
Tu Christine T.
Zegeer Jim
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