Integration of high k gate dielectric

Details Integration of high k gate dielectric Integration of high k gate dielectric

2006-04-11

2006-04-11

Lebentritt, Michael (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S508000, C438S585000, C438S591000, C438S785000

Reexamination Certificate

active

07026219

ABSTRACT:
Methods are provided herein for forming electrode layers over high dielectric constant (“high k”) materials. In the illustrated embodiments, a high k gate dielectric, such as zirconium oxide, is protected from reduction during a subsequent deposition of silicon-containing gate electrode. In particular, a seed deposition phase includes conditions designed for minimizing hydrogen reduction of the gate dielectric, including low hydrogen content, low temperatures and/or low partial pressures of the silicon source gas. Conditions are preferably changed for higher deposition rates and deposition continues in a bulk phase. Desirably, though, hydrogen diffusion is still minimized by controlling the above-noted parameters. In one embodiment, high k dielectric reduction is minimized through omission of a hydrogen carrier gas. In another embodiment, higher order silanes aid in reducing hydrogen content for a given deposition rate.

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