Method of forming a capacitor structure

Details Method of forming a capacitor structure Method of forming a capacitor structure

2000-06-07

2003-09-09

Tsai, Jey (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S003000, C438S770000

Reexamination Certificate

active

06617206

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to a capacitor structure and its method of manufacture. More particularly, the present invention relates to a capacitor structure for high-density memory arrays.
BACKGROUND OF THE INVENTION
Without limiting the scope of the invention, its background is described in connection with prior methods of forming capacitor structures for dynamic random access memory (DRAM) using high-dielectric-constant materials (or high-K dielectrics). By high-dielectric-constant, it is meant a dielectric constant greater than 10 at room temperature, and preferably a dielectric constant greater than 20.
Advances in miniaturization of integrated circuits have led to smaller areas available for devices 'such as transistors and capacitors. For example, in semiconductor manufacture of a memory array for a DRAM, each memory cell comprises a capacitor and a transistor. In a conventional DRAM, pairs of memory cells are located within regions (“memory cell, areas”) defined by intersecting row lines (“word lines”) and column lines (“bit lines” or “digit lines”). Accordingly, to increase memory cell density of the memory array, row lines and column lines are positioned with minimal spacing (“pitch”). Using minimal pitch in turn constrains memory cell area. In high-density memory array architecture, a memory array will have a bit line-to-bit line pitch equal to or less than 0.5 microns.
In conflict with reducing memory cell area is maintaining a sufficient amount of memory cell charge storage capacitance. Each DRAM memory comprises a capacitor for storing charge. A capacitor is two conductors separated by a dielectric, and its capacitance, C, is mathematically determinable as:
C
=(&egr;
r
&egr;
o
A
)/
d,
where &egr;
o
is a physical constant; dielectric constant, &egr;
r
, is a material dependant property; distance, d, is distance between conductors; and area, A, is common surface area of the two conductors.
To increase capacitance, C, per unit area, the DRAM industry is pursuing depositing materials with a high permittivity for use as capacitor dielectrics. Many perovskites, ferroelectrics, and other high-dielectric-constant materials have capacitance densities greater than standard silicon dioxide (SiO
2
) and silicon nitride (Si
3
N
4
) capacitor dielectrics.
Many perovskites have the chemical formula ABO
3
, where A is one or more monovalent, divalent, or trivalent elements and B is one or more pentavalent, tetravalent, trivalent, or divalent elements. Examples of high-dielectric-constant ferroelectric oxides include niobium pentoxide (Nb
2
O
5
); tantalum pentoxide (Ta
2
O
5
); and titanates including lead zirconate titanate (PbTiZrO
3
, abbreviated PZT) and barium strontium titanate (BaSrTiO
3
, abbreviated BST). Other high-dielectric-constant materials include but are not limited to non-oxide ferroelectrics, such as barium fluoride (BaF
2
) and magnesium fluoride (MgF
2
). Depending on the dielectric constant, &egr;
r
, of these materials, as well as the application, they may be used in parallel plate capacitor structures, such as stack capacitors or mini-stack capacitors, or vertical capacitor structures including container capacitors and trench capacitors.
High-dielectric-constant oxides are conventionally deposited in one step at elevated temperatures (greater than 500 degrees Celsius) in an oxygenated atmosphere (such as O
2
). Examples of processes for depositing high-dielectric-constant oxides are ion-beam sputtering, chemical vapor deposition, and pulsed laser deposition. It has been found that in such an environment, the capacitor electrode layer oxidizes, thereby causing an unwanted reduction in capacitance. Moreover, such high-dielectric-constant oxides are often annealed or re-oxidized after deposition, which further exacerbates the oxidation problem.
In addition, other problems may occur if high-dielectric-constant oxide dielectrics are deposited directly on silicon (Si) capacitor electrodes. In addition to oxidation or other undesirable reactions between the electrode and dielectric, silicon may migrate into the high-dielectric-constant oxide, thereby reducing its permittivity and the capacitor's capacitance.
One option to at least partially prevent these problems is to provide a barrier layer, such as a layer of germanium (Ge) or silicon nitride (Si
3
N
4
), between the silicon electrode and the high-dielectric-constant oxide. The oxidation conditions present after the deposition of this barrier layer may result in the oxidation of that layer, but this is actually preferable in certain circumstances. Regardless, it is desired in the art that this layer will prevent oxidation of the electrode. Unfortunately, the oxidation conditions in effect while forming the entirety of the high-K dielectric in one step often still cause oxidation of the silicon electrode despite the presence of the barrier layer. In addition, forming a barrier layer adds complexity to the manufacturing process and reduces the effective dielectric constant of the capacitor.
As an alternative to depositing dielectric on a silicon electrode, high-dielectric-constant oxides may be deposited on nonreactive metals or conductive metal oxides comprising the capacitor electrode. The term “nonreactive” when used in context with contact to a high-dielectric-constant oxide herein means a material that provides a stable conductive interface during and after processing. Examples of nonreactive metals include noble metals such as lead (Pd) or platinum (Pt). Exemplary conductive metal oxides include ruthenium oxide (RuO
2
). Single and multiple metal layers may used to form the capacitor electrode. However, while this solves some of the problems associated with silicon electrodes, the problem of oxidizing the electrode during or after the formation of the high-K dielectric still exists.
As a result, it would be desirable to form a high-dielectric-constant oxide such that the likelihood of decreasing capacitance is reduced.
SUMMARY OF THE INVENTION
Accordingly, the present invention provides a dielectric for a capacitor structure or other device, and method of formation thereof. Rather that provide a single layer of dielectric under a particular set of oxidation parameters, one exemplary embodiment of the current invention instead provides a plurality of thinner dielectric layers, wherein providing at least the layer nearest the capacitor electrode is accomplished under less aggressive oxidizing parameters. Such exemplary embodiments allow for greater control over the oxidation that may occur beyond the dielectric.


REFERENCES:
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patent: 5688724 (1997-11-01), Yoon et al.
patent: 5841186 (1998-11-01), Sun et al.
patent: 6172385 (2001-01-01), Duncombe et al.
patent: 6174564 (2001-01-01), Scott et al.
patent: 6307731 (2001-10-01), Katori

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