Fabricating plug and near-zero overlap interconnect line

Details Fabricating plug and near-zero overlap interconnect line Fabricating plug and near-zero overlap interconnect line

2000-02-18

2002-09-24

Clark, Sheila V. (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Physical configuration of semiconductor

Groove

C257S773000, C257S775000

Reexamination Certificate

active

06455921

ABSTRACT:

FIELD OF THE INVENTION
The invention relates generally to methods of fabricating semiconductor integrated circuits, and, more specifically, to methods of fabricating a vertically-extending metal plug connect to a horizontally-extending metal interconnect line.
BACKGROUND OF THE INVENTION
Referring to
FIG. 1
, a semiconductor integrated circuit generally has a structure consisting of a substrate on which a number of layers are fabricated. Lowermost are one or more semiconductor layers
12
in which a plurality of semiconductor devices and other electronic devices are fabricated. Next is a dielectric layer
14
, followed by an interconnect layer or metallization layer
16
. (Integrated circuits often include a number of alternating dielectric and metallization layers, but only one is shown here for sake of illustration.)
The interconnect layer
16
includes a plurality of interconnect lines or conductor lines
18
whose function is to electrically connect a first device on the semiconductor layer
12
to a second such device. A plug
20
extends vertically through the dielectric layer
14
to electrically connect the first device to the interconnect line
18
. The interconnect lines
18
and plugs
20
are fabricated of a material having high electrical conductivity, typically metal or doped semiconductor material.
After the semiconductor devices are fabricated in the semiconductor layer
12
, the remaining layers typically are fabricated by the following steps. First, a layer of dielectric
14
is deposited to cover the entire surface of the semiconductor layer
12
. Second, a vertical hole called a “via” is etched in the dielectric at each location where a plug is to be created. Third (optional), an extremely thin barrier layer and/or wetting layer
21
is deposited in each via. Fourth, a metal or other conductive material is deposited to fill each via to form the plugs
20
. Fifth, a blanket layer of metal or other conductive material is deposited over the substrate. The fourth and fifth steps may be performed as a single deposition step. Sixth, resist material is deposited and patterned over the blanket conductive layer so as to cover the areas of the conductive material which are to become the interconnect lines. Finally, the blanket conductive layer is etched to remove the conductive material from all surfaces not covered by resist, thereby creating the interconnect lines.
A problem with conventional processes for forming an interconnect line is that the process of etching the edge
22
of the interconnect line can undesirably etch part of the plug
20
, creating a void
24
in the plug as shown in
FIGS. 2A and 2B
. Such voids can be created when the etching process is continued too long (see FIG.
2
A), or when the interconnect line is misaligned relative to the plug so that one edge
22
of the interconnect line is too close to, or fails to overlap, the adjacent edge of the plug (see FIG.
2
B).
The risk of creating voids caused by over-etching or misalignment is highest if the interconnect line is no wider than the plug, i.e., a “zero overlap” interconnect, as shown in FIG.
2
A. However, “zero overlap” interconnect lines are desirable to maximize the density of components on an integrated circuit. Therefore, methods have been developed to prevent voids in plugs beneath “zero overlap” interconnects.
One conventional method of preventing the interconnect etch process from etching into the plug is to fabricate the plug and interconnect lines of different materials. The edge of the interconnect then can be chemically etched using an etchant which does not significantly etch the plug material. Specifically, plugs and interconnect lines conventionally are fabricated of tungsten and aluminum, respectively. Chlorine is much more reactive with aluminum than with tungsten. Therefore, the edges of the aluminum interconnects can be etched with chlorine without significantly etching the tungsten plugs.
However, the method described in the preceding paragraph is disadvantageous in at least two respects. One disadvantage is that it precludes using the best conductor material for both the plugs and the interconnects. Specifically, aluminum is the preferred material for both the plugs and the interconnect lines because aluminum has a higher conductivity (lower resistivity) than other materials conventionally used for fabricating plugs, such as tungsten. Another disadvantage is that the contact between two different plug and interconnect materials can be unreliable.
When both the plugs and the interconnect lines are fabricated of the same material, such as aluminum, a conventional method of preventing the interconnect etch process from creating a void in the plug is to compromise the goal of “zero overlap” interconnect lines. Specifically, the interconnect lines are fabricated with extra width (labelled as “X” in
FIG. 1
) overlapping the dielectric on all sides of the plug, so that a certain amount of excessive etch time or misalignment between the interconnects and the plugs can be tolerated without etching into the plug. Of course, a disadvantage of this method is that the overlap “X” wastes space on the integrated circuit, thereby reducing the number of semiconductor devices which can be fabricated on an integrated circuit having a given surface area.
SUMMARY OF THE INVENTION
The invention is an integrated circuit including an electrically conductive plug having a narrow neck, and a method of fabricating such plug and an overlying interconnect conductor. The invention prevents the etching of the interconnect from creating a void in the plug. The plug is fabricated by creating in the dielectric layer a cavity or via having an inwardly-extending lateral protrusion near the mouth of the cavity. The overlying interconnect is created by depositing a layer of conductive material and then etching the layer on two opposing sides of the plug. During etching of the layer, the protrusion advantageously prevents any etching of the metal plug beyond the protrusion, thereby preventing the etching from creating voids in the plug.
The invention permits the overlying interconnect to be fabricated more narrowly, i.e., with less overlap over the dielectric surrounding the plug, thereby improving the density of the integrated circuit.
The invention is particularly advantageous when the plug and interconnect are fabricated of the same conductive material, such as aluminum.


REFERENCES:
patent: 4676869 (1987-06-01), Lee et al.
patent: 5364817 (1994-11-01), Lur et al.
patent: 5460689 (1995-10-01), Raaijmakers et al.
patent: 5470790 (1995-11-01), Myers et al.
patent: 5612252 (1997-03-01), Lur et al.
patent: 5698112 (1997-12-01), Naeher et al.
patent: 5773537 (1998-06-01), Shishiguchi
patent: 5851923 (1998-12-01), Rolson
patent: 5874357 (1999-02-01), Jun et al.
patent: 6107196 (2000-08-01), Rolfson
patent: 6187659 (2001-02-01), Ying et al.
patent: 1-286442 (1989-11-01), None
patent: 95/28000 (1995-10-01), None
“Method of anchoring contact or via plugs by producing lateral recess in ILD or IMD films”, IBM Tech. Disc. Bull., vol. 38, No. 6, Jun. 1995, pp. 405-407.
S.M. Rossnagel & J. Hopwood, “Metal ion deposition from ionized magnetron sputtering discharge,” Jan./Feb. 1994, J. Vac. Sci. Technol. B 12 (1), pp. 449-453.

Affiliated with

Also associated with

Rating

Fabricating plug and near-zero overlap interconnect line does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Fabricating plug and near-zero overlap interconnect line, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Fabricating plug and near-zero overlap interconnect line will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2913569