Sheila V. Clark

Examiner

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60 degree bump placement layout for an integrated circuit...

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Configuration or pattern of bonds
Reexamination Certificate

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90 degree bump placement layout for an integrated circuit...

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Configuration or pattern of bonds
Reexamination Certificate

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Active organic semiconductor devices and methods for making...

Semiconductor device manufacturing: process – Having organic semiconductive component
Reexamination Certificate

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Al/Ti layered interconnection and method of forming same

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Patent

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Alignment-marker structure and method of forming the same in int

Active solid-state devices (e.g. – transistors – solid-state diode – Alignment marks
Patent

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Profile ID: LFUS-PAI-P-141476

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