Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1999-06-04
2002-08-27
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
Reexamination Certificate
active
06442720
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to testing of integrated circuit (IC) chips, and more particularly to failure analysis of semiconductor IC chips. More particularly, this invention relates to an improved testing technique for testing IC chips using picosecond imaging circuit analyzer(PICA)techniques.
TRADEMARKS
S/390 and IBM are registered trademarks of International Business Machines Corporation, Armonk, N.Y., U.S.A. and Lotus is a registered trademark of its subsidiary Lotus Development Corporation, an independent subsidiary of International Business Machines Corporation, Armonk, N.Y. Other names may be registered trademarks or product names of International Business Machines Corporation or other companies.
BACKGROUND
Very large scale integration (VLSI) logic integrated circuit (IC) chips, e.g. microprocessors, contain very large numbers of logic circuits. Testing the many logic circuits in a chip is an important part of the manufacturing process of the chip.
Logic circuits typically include many interconnected logic gates. The various logic gates include, e.g., “AND” gates, “OR” gates, “NAND” gates, “NOR” gates, “NOT” gates, “XOR” gates and so on. A logic circuit has a number of inputs for receiving data, and a number of outputs for outputting data. The logic circuit is designed such that for each input pattern, of a set of one or more input patterns, provided at the inputs of the logic circuit, a corresponding predetermined output pattern is produced at the outputs of the circuit.
If there is a fault or defect in the logic circuit, then for one or more input patterns provided at the inputs of the circuit, the observed output patterns produced at the outputs of the circuit will differ from the expected predetermined output patterns.
One way to test for faults in a logic circuit is to apply each possible input pattern at the inputs of the logic circuit, and to compare the actual output pattern with the expected output pattern. For small numbers of possible input patterns, the cost of storing the expected output patterns and performing this deterministic testing is reasonable. However, for large numbers of possible input patterns, the cost of such deterministic testing is too high.
An alternative method of testing for faults in a logic circuit applies random input test patterns at the inputs of the logic circuit, and compares the actual output patterns with the expected output patterns. The number of random test patterns needed to achieve a selected level of confidence that a logic circuit contains no faults depends on the circuit design.
Another alternative method of testing for faults in a logic circuit applies one or more weighted random input test patterns at the inputs of a logic circuit, and compares the actual output patterns with the expected output patterns. The weights may be uniform across all digits in the test pattern, or the weights may be nonuniform. The weighted random test patterns are selected to achieve, efficiently and at a low cost, a desired level of confidence that the logic circuit contains no faults.
As integrated circuit chip devices have become more densely packed with electronic components and more complex, the need for effectively testing such circuits has become more important. This is especially true of digital logic circuits. In order to provide a mechanism for testing complex circuitry of this type, a number of built-in self test (BIST) methodologies have been employed including level sensitive scan design (LSSD) techniques. LSSD design can be performed in accordance with the teachings of “Level Sensitive Logic System,” U.S. Pat. No. 3,783,254, and “Method of Level Sensitive Testing A Functional Logic System,” U.S. Pat. No. 3,761,695, both to Edward B. Eichelberger and of common assignee to this invention, the contents of which are incorporated herein by reference in their entireties.
In the LSSD methodology, a long string of shift register latches (SRLs) is employed in a dual function role which does not detract from normal circuit operation. In particular, a shift register (SR) string provides normal input during circuit operation and provides a mechanism for providing test input signals to the circuit for testing purposes. These tests may be employed, for example, immediately subsequent to chip manufacture, and in field test error conditions. Depending on the source of input signals to the SRL scan string, either normal operations or test operations can be carried out.
An important concept for grasping the present invention, is the notion of a “cone of logic.” In any given logic circuit, there are input and output signal lines. Not every input line can generally influence every output signal line. Conversely, each output signal line is generally capable of being influenced only by a subset of input signal lines. Thus, each output signal line is associated with a cone of logic representing signal paths through which input signals influence the output signal. Furthermore, an input signal line can influence the output at more than one output signal line. Thus, one can associate with each output signal line a subset of input signal lines passing through and defining the cone of logic. One can associate with each input signal line a subset of output signal lines which can be influenced by the input signal present on any selected input signal line. For further discussion of logic cones, the reader is referred to “Delay Test Coverage Enhancement for Logic Circuitry Employing Level Sensitive Scan Design,” U.S. Pat. No. 5,278,842, to Edward B. Eichelberger of common assignee to this invention, the contents of which is incorporated herein by reference in its entirety.
An example testing technique of VLSI logic chips, i.e. microprocessors, using pseudo-random pattern generation techniques, is logic built-in self test (LBIST). LBIST initializes a set of latches and generates a set of pseudo-random latch value patterns for all latches in a chip. A clock pulse scans the test pattern and the output is then compared to an expected result. Thereafter, a new set of latch values can be loaded into the latches. For further information regarding LBIST techniques, the reader is referred to “Self-Testing of Multichip Modules,” by P. H. Bardell and W.H. McAnney, in Proceedings of the IEEE International Test Conference, 1982, pages 200-204, the contents of which is incorporated herein by reference in its entirety.
Weighted random pattern (WRP) testing uses circuitry added to a pseudo-random number generator to weight the inputs to the device under test to produce a greater number of ones or zeros. WRP is described at length in “Weighted Random Pattern Testing Apparatus and Method,” U.S. Pat. No. 4,688,223, to Franco Motika and John A. Waicukauski, of common assignee to this invention, the contents of which is incorporated herein by reference in its entirety.
A new circuit testing technique called picosecond imaging circuit analyzer (PICA) captures weak, transient light pulses that are emitted by individual switching transistors through the backside of the chip. Airline passengers on a night flight can see the traffic of cities beneath them traced out by illumination from vehicles' headlights. In much the same way, chip designers using PICA can use light emitted by speeding electrons to examine the activity of circuits in computer chips. Electronic engineers can use PICA to spot problems in their circuit designs and manufacturing processes, and to debug chips.
Scientists have known since the 1980s that electrons emit light known as photons when they speed through field effect transistors (FETs), the building blocks of complementary metal-oxide-semiconductor (CMOS) microchips. Microprocessors and memory chips can be made from CMOS circuits. The electrons move only when the CMOS circuits change from one state to another, switching on or off. Detecting these very faint light emissions can be used to monitor the switching of individual components of advanced CMOS chips.
High-speed optical detectors can be used to monitor light emissions from si
Koprowski Timothy J.
Kusko Mary P.
Rizzolo Richard F.
Song Peilin
Augspurger Lynn
Cantor & Colburn LLP
International Business Machines - Corporation
Lamarre Guy
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