Parallel bit test apparatus and parallel bit test method...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing

Reexamination Certificate

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C365S201000

Reexamination Certificate

active

07941714

ABSTRACT:
A parallel bit test (PBT) apparatus, included in memory chips that are stacked in a multi-chip package (MCP) and that share a set of data signal lines, may include: a comparing unit to output a data signal representative of a comparison between test data signals provided to a given one of the memory chips and corresponding data signals output therefrom, respectively; and a coding unit to output the representative data signal using a first subset of the shared set of data signal lines, the first subset not overlapping other subsets used by coding units corresponding to the other ones of the memory chips, respectively, the coding unit selecting one or more of the data signal lines amongst the shared set of data signal lines for inclusion in the first subset according to a first test mode register set (MRS) signal.

REFERENCES:
patent: 5471480 (1995-11-01), You
patent: 6263141 (2001-07-01), Smith
patent: 6788596 (2004-09-01), Kim et al.
patent: 6845478 (2005-01-01), Luong
patent: 7036058 (2006-04-01), Miyachi et al.
patent: 7546506 (2009-06-01), Sonoda et al.
patent: 2003/0043664 (2003-03-01), Haraguchi et al.
patent: 2007/0011518 (2007-01-01), Ung et al.
patent: 93-22382 (1993-11-01), None
patent: 10-2001-0049778 (2001-06-01), None
patent: 10-2002-0002943 (2002-01-01), None
patent: 10-2004-0070924 (2004-08-01), None
patent: 10-2004-0080552 (2004-09-01), None
Zorian, Y.; , “Multi-chip module technology,” Neural Networks, 1995. Proceedings., IEEE International Conference on , vol. 1, No., pp. 152-157 vol. 1, Nov./Dec. 1995 doi: 10.1109/ICNN.1995.488084.
Lin, T.-T.Y.; Comito, J.; Kaseff, C.; , “Evaluation of test strategies for multichip modules,” ASIC Conference and Exhibit, 1992., Proceedings of Fifth Annual IEEE International , vol., No., pp. 234-237, Sep. 21-25, 1992 doi: 10.1109/ASIC.1992.270269.
Round, B.J.; , “Manufacturing defects testing of a multi-chip-module using IEEE 1149.1 boundary scan test and embedded built-in test software,” Autotestcon '93. IEEE Systems Readiness Technology Conference. Proceedings , vol., No., pp. 151-156, Sep. 20-23, 1993 doi: 10.1109/AUTEST.1993.396355.

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