Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1997-11-25
2001-01-23
Fahmy, Wael (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S768000, C438S786000, C438S954000
Reexamination Certificate
active
06177311
ABSTRACT:
FIELD OF THE INVENTION
The invention relates generally to nonvolatile floating gate memory devices and, more specifically, to an improved interpoly dielectric for floating gate memory devices and associated fabrication processes.
BACKGROUND OF THE INVENTION
Floating gate memory devices, such as Erasable Programmable Read Only Memory (EPROM), Electrically Erasable Programmable Read Only Memory (EEPROM) and Flash EPROMs or EEPROMs, are widely used for nonvolatile memories. These devices store charges in a floating gate. The floating gate must hold a charge without refresh for extended periods. The floating gate is charged by hot electron or avalanche injection through a gate oxide between the floating gate and the substrate. Typically, a first layer of polysilicon is used for the floating gate, which is a totally encapsulated and electrically isolated portion of polysilicon. The control gate is formed over the floating gate in a second layer of polysilicon. The floating and control gates are separated by an interpoly dielectric and act as two plates of a capacitor. Transistor source and drain regions are formed below and adjacent to the floating gate.
For a flash cell, the floating gate may be charged by applying a relatively large voltage to the control gate. The voltage on the control gate establishes an electric field in the gate oxide between the floating gate and the substrate. Then a lower voltage pulse is applied between source and drain regions in the substrate. The electric field attracts the electrons generated from the “avalanche” breakdown of the transistor due to the drain and control gate voltages and injects those electrons into the floating gate through the gate oxide. This process of injection charging is referred to as hot electron or avalanche injection.
As the cell spacing of floating gate memory devices is reduced, a very high quality interpoly dielectric is needed to maintain high specific capacitance between the floating gate and the control gate. This dielectric must perform effectively during the application of high charging voltages and also prevent leakage between the floating gate and the control gate after charging. Since information is stored without refresh by charges trapped in the floating gate, it is critical that leakage between the floating gate and the control gate be minimized.
For standard Metal Oxide Silicon (MOS) processes, forming a precision capacitor over a first layer of polysilicon is difficult since the surface of the polysilicon is not as smooth as that of the polished surface of the substrate. The unevenness of the polysilicon can significantly affect the thickness of an oxide insulator formed over the polysilicon. Variations in thickness of an oxide leads to corresponding variations in the specific capacitance between the gates.
U.S. Pat. No. 4,613,956 issued to Patterson et al. on Sep. 23, 1986 presents one solution to the above-referenced problems. Patterson describes an integrated insulating dielectric comprising a composite oxide
itride or oxide
itride/oxide dielectric insulator used over the first layer of polysilicon instead of the thermally grown oxide previously used. The composite dielectric disclosed in Patterson has come to be commonly referred to as an “ONO” film stack. The present invention provides an alternative and equally effective interpoly dielectric to the ONO film stack described in Patterson.
SUMMARY OF THE INVENTION
One object of the invention is to provide a floating gate memory having a high specific capacitance between the floating gate and the control gate, even at reduced cell spacing on the order of 1.0 micron.
It is another object of the invention to provide a floating gate memory in which the specific capacitance and leakage resistance between the floating gate and the control gate is very high.
It is another object of the invention to provide a method for fabricating a floating gate memory in which the interpoly dielectric has a uniform thickness.
According to the present invention, these and other objects and advantages are achieved by a floating gate memory device utilizing a composite oxide/oxynitride or oxide/oxynitride/oxide interpoly dielectric. The dielectric comprises a layer of silicon dioxide and a discrete layer of silicon oxynitride formed on the layer of silicon dioxide. Alternatively, the intergate dielectric comprises a layer of silicon dioxide formed over the layer of oxynitride to form a composite oxide/oxynitride/oxide film stack. The composite oxide/oxynitride film stack allows for high specific capacitance and high leakage resistance between the floating gate and the control gate. Another aspect of the invention provides a method of fabricating a floating gate memory device incorporating the oxide/oxynitride interpoly dielectric. The method comprises the steps of: (1) forming a floating gate; (2) forming a control gate over the floating gate; and (3) forming a dielectric between the floating gate and the control gate. The step of forming the dielectric includes forming a discrete layer of silicon oxynitride on a layer of silicon dioxide.
The oxynitride used in the present invention is itself a separate and distinct compound. For instance, some processes oxidize the silicon nitride and this oxidized film is referred to as oxynitride. In the present invention, by contrast, the oxynitride film is a separate and distinct compound deposited over the underlying layer of silicon dioxide. In that aspect of the invention having a composite three stack film, the second layer of silicon dioxide is formed directly over the silicon oxynitride. The use of oxynitride as an alternative to nitride results in comparable performance. Nitride has a refractory index of approximately 2.0 while oxynitride has a refractory index in the range of 1.84 to 1.95.
Other objects, advantages and novel features of the invention will become apparent to those skilled in the art upon examination of the following detailed description or may be learned by practice of the invention. The objects and advantages of the invention may be realized and achieved by means of the instrumentalities and combinations particularly pointed out in the appended claims.
REFERENCES:
patent: 4438157 (1984-03-01), Romano-Moran
patent: 4613956 (1986-09-01), Paterson et al.
patent: 4618541 (1986-10-01), Forouhi et al.
patent: 4697330 (1987-10-01), Paterson et al.
patent: 4937756 (1990-06-01), Hsu et al.
patent: 4980307 (1990-12-01), Ito et al.
patent: 5010024 (1991-04-01), Allen et al.
patent: 5063431 (1991-11-01), Ohshima
patent: 5256584 (1993-10-01), Hartman
patent: 5306936 (1994-04-01), Goto
patent: 5414287 (1995-05-01), Hong
patent: 5674788 (1997-10-01), Wristers et al.
patent: 5780891 (1998-07-01), Kauffman
S. Lim et al., Inhomogeneous dielectrics grown by plasma-enchanced chemical vapor deposition, Thin Solid Films, vol. 236 (1993), pp. 64-66, Oct. 1993.
A. Sassella et al., Silicon oxynitride study by the tetrahedron model and by spectroscopic ellipsometry, Journal of Non-Crystalline Solids, vol. 187, pp. 396-402, Jul. 1995.
Kauffman Ralph
Lee Roger
Coleman William David
Fahmy Wael
Micro)n Technology, Inc.
Ormiston & McKinney PLLC
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