Method for making a trench-free buried contact with low resistan

Details Method for making a trench-free buried contact with low resistan Method for making a trench-free buried contact with low resistan

1997-04-09

1999-07-20

Chaudhari, Chandra

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438525, 438586, H01L 218244

Patent

active

059267062

ABSTRACT:
A method is achieved for forming buried contacts with diffused contact regions on semiconductor integrated circuits having low sheet resistance between the buried contacts and the field effect transistors. The method also allows for greater misalignment tolerances that prevent trenching or electrical opens from occurring in the diffused contact regions when etching the polycide interconnecting lines over the contacts. The method utilizes the etch back of an opening in the photoresist contact mask and a subsequent angular implant to extend the diffused contact regions to reduce the sheet resistance between the buried contacts and the FETs. The method is especially useful for electrically connecting the drain of the pass transistor to the gate of the pull-down transistor on static RAM devices.

REFERENCES:
patent: 5177030 (1993-01-01), Lee et al.
patent: 5240874 (1993-08-01), Roberts
patent: 5292676 (1994-03-01), Manning
patent: 5378641 (1995-01-01), Cheffings
patent: 5543350 (1996-08-01), Chi et al.
patent: 5550085 (1996-08-01), Liu

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