Write assist circuit for improving write margins of SRAM cells

Details Write assist circuit for improving write margins of SRAM cells Write assist circuit for improving write margins of SRAM cells

2011-03-01

2011-03-01

Nguyen, Tuan T. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C365S189160, C365S185230, C365S189020

Reexamination Certificate

active

07898875

ABSTRACT:
A memory circuit includes a memory array, which further includes a plurality of memory cells arranged in rows and columns; a plurality of first bit-lines, each connected to a column of the memory array; and a plurality of write-assist latches, each connected to one of the plurality of first bit-lines. Each of the plurality of write-assist latches is configured to increase a voltage on a connecting one of the plurality of first bit-lines.

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