Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1999-05-19
2002-11-26
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C324S762010, C326S068000
Reexamination Certificate
active
06487687
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates generally to the field of electronic circuits, and more particularly to a level shifter providing testability.
BACKGROUND OF THE INVENTION
Modern ICs often interface with complementary metal-oxide semiconductor (CMOS) voltage levels on chips from previous technology generations. In order to interface with such voltage levels, ICs must include output buffers capable of driving high to an output much greater than the source voltage.
Many output buffer circuits are coupled to one or more power supplies and use output drivers to switch an output voltage according to the values of one or more inputs. For example, an output buffer that receives a high voltage (VDDHV) from a first power supply and an internal chip core voltage (VCG) from a second power supply might have p-channel and n-channel output drivers to switch an output voltage according to values of a data input and an enable input. Typically, output buffers have only a single thin gate oxide. The single thin gate oxide becomes overstressed by a gate-drain voltage much above the source voltage. It is often desirable to protect the gate oxides of these output drivers and other components of the output buffer from overstress, breakdown or other damage due to changes in voltage on the output. Typically, the gate oxide of a transistor can withstand DC voltages only up to approximately VCG plus a transistor threshold voltage (VT).
As microelectronic devices become increasingly complex to satisfy additional processing requirements, reducing the failure of devices during operation becomes increasingly important. A known technique for protecting the gate oxide of output drivers includes coupling cascode devices in series with the output drivers, and in a level shifter, to turn off the switching output P-driver. The cascode devices are supposed to prevent their drains from being pulled past their gate potentials and overstressing the gate oxides of neighboring devices. The cascode devices thus shield the gate oxide of the output driver from voltage levels on the output. The gate of the cascode is maintained at a substantially constant intermediate voltage, such that the voltage across the gate oxide does not exceed the gate oxide's maximum fixed voltage tolerance.
Although these techniques protect the output driver gate oxide when the cascode devices are functioning properly, the output driver is susceptible to oxide stress and failure if the cascode devices in the level-shifter are shorted, even though the output buffer may appear to be functioning properly. Furthermore, such techniques do not provide for detection of cascode failure, leaving previous output buffers and the associated electronic devices prone to unexpected failure during operation. These and other inadequacies make existing output buffers and associated level shifters unsuitable for many applications.
SUMMARY OF THE INVENTION
Therefore, a need has arisen for a level shifter output buffer that addresses the disadvantages and deficiencies of previous systems.
A method for testing a level shifter having a plurality of cascode devices is disclosed. According to one embodiment of the present invention, the level shifter is operable to couple a data input and an enable input to an output buffer and operable to receive a first voltage from a first reference supply and a second voltage from a second reference supply. A first testability device is coupled to a cascode device of the level shifter and to a substantially constant test reference supply. A test current is detected in response to failure of the cascode device.
The level shifter and method of the present invention provide a number of technical advantages. The level shifter includes one or more testability devices that each correspond to a cascode device of the level shifter. Each testability device generates current in response to failure of the corresponding cascode device to indicate failure of the cascode device. The current is detectable as increased or decreased current on an associated reference supply. Since the cascode devices of the level shifter protect the gate oxides of the corresponding devices of the level shifter, respectively, and since the failure of any one of these cascodes will leave the output buffer and associated electronic device susceptible to failure during operation, providing for testability of the condition of the output buffer is a technical advantage.
Another technical advantage of the present invention is that the testability devices pass current sufficient for test detection. Another technical advantage is that the invention can detect multiple failures of cascode devices by providing detectable current on an upper power supply.
REFERENCES:
patent: 4345217 (1982-08-01), Pace
patent: 5524094 (1996-06-01), Nobukata et al.
patent: 5764077 (1998-06-01), Andresen et al.
patent: 5995010 (1999-11-01), Blake et al.
patent: 6100716 (2000-08-01), Adham et al.
patent: 6211693 (2001-04-01), Andresen et al.
08/516,514, “High Voltage Tolerant Output with Enhanced Testability and Reliability,” filed Aug. 17, 1995, Under Appeal (not included) (abandoned).
Andresen Bernhard H.
Blake Terence G. W.
Wall Frederick G.
Brady III W. James
De'cady Albert
Lamarre Guy
Marshall, Jr. Robert D.
Telecky , Jr. Frederick J.
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