Vertical dual gate field effect transistor

Details Vertical dual gate field effect transistor Vertical dual gate field effect transistor

2007-02-13

2007-02-13

Wilczewski, M. (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S173000, C438S212000, C438S283000

Reexamination Certificate

active

10853177

ABSTRACT:
A method of manufacturing provides a vertical transistor particularly suitable for high density integration and which includes potentially independent gate structures on opposite sides of a semiconductor pillar formed by etching or epitaxial growth in a trench. The gate structure is surrounded by insulating material which is selectively etchable to isolation material surrounding the transistor. A contact is made to the lower end of the pillar (e.g. the transistor drain) by selectively etching the isolation material selective to the insulating material. The upper end of the pillar is covered by a cap and sidewalls of selectively etchable materials so that gate and source connection openings can also be made by selective etching with good registration tolerance. A dimension of the pillar in a direction parallel to the chip surface is defined by a distance between isolation regions and selective etching and height of the pillar is defined by thickness of a sacrificial layer.

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