Transistor, memory cell array and method of manufacturing a...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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Details

C438S270000, C257SE21540

Reexamination Certificate

active

07132333

ABSTRACT:
A transistor, memory cell array and method of manufacturing a transistor are disclosed. In one embodiment, the invention refers to a transistor, which is formed at least partially in a semiconductor substrate, comprising a first and a second source/drain regions, a channel region connecting said first and second source/drain regions, said channel region being disposed in said semiconductor substrate, and a gate electrode disposed along said channel region and being electrically isolated from said channel region, for controlling an electrical current flowing between said first and second source/drain regions, wherein said channel region comprises a fin-region in which the channel has the shape of a ridge, said ridge comprising a top side and two lateral sides in a cross section perpendicular to a line connecting said first and second source/drain regions, wherein said top side is disposed beneath a surface of said semiconductor substrate and said gate electrode is disposed along said top side and said two lateral sides.

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patent: 6838342 (2005-01-01), Ding
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patent: 2005/0285153 (2005-12-01), Weis et al.
patent: 10220542 (2002-05-01), None
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patent: 102004031385 (2006-01-01), None
patent: 1017095 (2000-07-01), None

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